Thomson-csf

Applied Materials, Inc.

Thomas P Pearsall

Lawrence Camest West

Stephen Moffatt

Francisco A Leon

Gregory L Wojcik

Daniel Delagebeaudeuf

A planar integrated circuit includes a semiconductor substrate having a substrate surface and a trench in the substrate, a waveguide medium in the trench having a top surface and a light propagation axis, the trench having a sufficient depth for the waveguide medium to be at or below said substrate surface, and at least one Schottky barrier electrode formed on the top surface of said waveguide medium and defining a Schottky barrier detector consisting of the electrode and the portion of the waveguide medium underlying the Schottky barrier electrode, at least the underlying portion of the waveguide medium being a semiconductor and defining an electrode-semiconductor interface parallel to the light propagation axis so that light of a predetermined wavelength from said waveguide medium propagates along the interface as a plasmon-polariton wave.

Planar integrated circuit including a plasmon waveguide-fed Schottky barrier detector and transistors connected therewith

An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.

Impurity-based waveguide detectors

A heterojunction semiconductor device comprising an active zone made from a ternary or quaternary alloy of the Ga In As P type and resting via a buffer layer of similar composition on a substrate in such a way that the active layer and the buffer zone have similar expansion coefficients.

Heterojunction semiconductor device

A photodiode comprising a first layer of a relatively large forbidden band (e.g. 1.4 eV) in a p type of conductivity, wherein photons can be absorbed, thus creating pairs of electron-holes diffusing towards a second layer, said second layer having a forbidden band. (0.7 eV) that is approximately half of the first band. In that second layer of an n-type of conductivity each electron falls and creates by impact ionization a new pair electron-hole, thus producing an avalanche gain of 2. The phenomenon occurs theoretically with a zero bias voltage. In practice the photodiode operates with a bias voltage near zero. The two materials of the heterojunction are for instance In P (forbidden band: 1.4 eV) and Ga.sub.0.47 In .sub.0.53 As (0.7 eV) providing crystalline networks perfectly matched.

Heterojunction photodiode of the avalanche type

In an avalanche diode of gallium arsenide, e.g. an IMPATT diode, the optimization of the coefficient of ionization by impact in the case of impacts initiated by holes when the electrical field propels the carriers along the axis of 1 1 1 of the monocrystal, has been utilized. The structure comprises a substrate of Ga As with two large faces perpendicular to the axis 1 1 1 and layers obtained by epitaxial growth from one of these large faces. Arrangements are made to ensure that the electrical field is as parallel as possible to this crystalline axis. The improvement in efficiency is of the order of 20%.

(III) Plane gallium arsenide IMPATT diode

An avalanche diode comprising a semiconducting heterojunction (Ga.sub.x In.sub.1-x As/InP) intended to oscillate as an 'IMPATT' diode. It comprises a substrate of n.sup.+ doped monocrystalline InP supporting a series of three layers which are formed by epitaxy and of which the monocrystalline latices match one another namely an InP layer with n-type doping and two layers of Ga.sub.x In.sub.1-x As (best mode: Ga.sub.0.47 In.sub.0.53 As) with n-type and p.sup.+ -type doping respectively, these two layers being of minimal thickness. When a backward bias is applied to the p.sup.+ n-junction, the avalanche phenomenon takes place in the thin n-type layer of ternary alloy.

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Thomas P Pearsall