International Business Machines Corporation

Thomas P Lanzoni

Jorge Gonzalez-Lopez

James Anthony Pafumi

Robert Spencer Horton

William Alan Wall

Jeffrey Allan Whaley

Ashu Kohli

James Aloysius Donnelly

William L Luken, Jr

Joseph J Ellis, Jr

Richard P Carini

Christopher Edward Koob

A computer system has a graphics subsystem employing a rasterizer and a frame buffer, with a digital-to-analog converter for producing drive signals to a video display. A bus interface acts as a gateway between a PCI bus and the graphics subsystem; this interface manages commands and DMAs passing between the host processor and various parts of the graphics subsystem. Within the interface, two command FIFOs are employed, one for storing commands/data sent from the host for 2D display (window management) and another for 3D applications. Using two command FIFOs eliminates the need for host semaphore, FIFO draining, and the latency associated with these operations. Timers are provided in the interface, associated with the two command FIFOs, to manage and regulate the frequency with which the system automatically switches between 2D and 3D FIFO processing. Host intervention is minimized by use of a context macro store for holding locally the sequences for context save and context restore which are used repeatedly.

Computer graphics system with dual FIFO interface

In a computer graphics display system, a method and processor are disclosed for drawing one of a concave polygon, self-intersecting polygon and polygon with polygonal hole. Pursuant to the method, a mask buffer organized into an M.times.N plurality of addressable constituent pixels is used. The method includes the steps of: masking the pixels of the mask buffer corresponding to the boundary of the polygon and drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; masking the pixels in the mask buffer corresponding to the interior of the polygon while preserving the masked pixels in the mask buffer corresponding to the polygon boundary; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the masked polygon interior pixels in the mask buffer. Further processing steps include: tessellating the polygon into a set of triangles; determining the orientation of each of the triangles definitive of the decomposed polygon; and processing the pixels in the mask buffer corresponding to the interior of each triangle such that interior pixels of adjacent triangles of the same orientation are masked while interior pixels of adjacent triangles of different orientation are unmasked within the triangles' region of overlap. Specific algorithms are described for the above masking and drawing steps. In addition, a display processor implementing the described method is also provided.

Concave polygon drawing method and processor for a computer graphics

In a computer graphics display system, a method and processor are disclosed for drawing a `polygon with edge`-type primitive encountered in certain high level graphics interface programs. Both the method and processor use a mask buffer organized into a plurality of addressable constituent pixels, each pixel preferably being two bits deep. The method includes: masking the pixels in the mask buffer corresponding to the boundary to the polygon; drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the content of the mask buffer. Corresponding processing steps for writing Z values in a depth buffer are also described. In addition, specific algorithms for implementing the method are set forth, along with an embodiment of a display processor implementing the method.

Method and processor for drawing `polygon with edge`-type primitives in

Z-buffer control logic that provides access AND comparison at speeds unconstrained by DRAM memory access times. A Z-buffer controller is implemented which accumulates a number of pixels in adjacent locations into an associated cell. A Z-buffer comparator accesses Z-buffer retained values for the cell in parallel, performs parallel comparisons, and passes the results to a serializer. The Z-buffer serializer returns the order of the written pixels and outputs the required values to a display interface for continued processing and display on a graphics display device.

High speed Z-buffer control

A multi-window display station having main frame (host) interactive and local personal computer display data buffers is provided. The outputs of the two data buffers are merged, using a row or swath buffer, according to default or escape codes stored in one of the data buffers and the combined output drives a plasma panel display. Registers for modified data tags and for presence/absence of escape codes speed the panel update process. Means are included to provide alpha-numeric and graphic windows together on the panel screen.

Growing community of inventors

Lake Katrine, NY, United States of America

Thomas P Lanzoni