United States of America As Represented by the Administrator of Nasa

Thomas P Flatley

David J Petrick

Alessandro D Geist

Gary A Crum

Christopher Wilson

Nicholas Franconi

Cody Brewer

Milton C Davis

Daniel C Espinosa

Manuel Buenfil

Semion Kizhner

Robin A Ripley

Dominic J Benford

Katherine R Heinzen

Maxime Pinchinat

Jeffrey C Hosler

Alessandro Giest

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Processor card and intelligent multi-purpose system for use with processor card

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards

A single-board computer system radiation hardened for space flight includes a printed circuit board (PCB) having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side, wherein AC coupling capacitors are configured to select routing between the first FPGA and the second FPGA. An expansion card plug attaches to a connector on the bottom of the PCB and a frame is mounted to the PCB.

SpaceCube V3.0 single-board computer

An improved method for correcting for noise in the digital domain is disclosed. Reference pixel fast-varying components are extracted using a Hilbert-Huang Transform Real-Time Data Processing System (HHT-DPS-RT). The reference pixels are non-photon-detecting pixels in a sensor array. The fast-varying components of the reference pixels are processed in addition to the average over the remaining trend, facilitating additional noise correction for active pixels.

Reducing sensor and readout circuitry noise in digital domain using reference pixels

A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Radiation-hardened processing system

Growing community of inventors

Huntington, MD, United States of America

Thomas P Flatley