Advanced Micro Devices Corporation

Microelectronics and Computer Technology Corporation

Other

Thomas P Dolbear

Richard D Nelson

Sanjay Dandia

Dennis J Herrell

Daniel Cavasin

Michael A Olla

Seyed H Hashemi

Colin A MacKay

Robert W Froehlich

David A Gibson

Omkarnath R Gupta

Doug Markwardt

Lewis M Eyman

An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Back side metallization

An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.

Low inductance power distribution system for an integrated circuit chip

A temperature sensor for an integrated circuit is attached to a heat sink using a compliant member such as a spring. The spring attaches to the heat sink and extends across a slot in the thermal contact surface of the heat sink so that the temperature sensor coupled to the spring is centered nominally over an integrated circuit die when the heat sink is abutted against the integrated circuit.

Temperature sensor mounting for accurate measurement and durability

An arrangement for a motherboard having a connector for a removable module is disclosed which increases the aggregate current carrying capacity of the connector by reducing the difference in current flow between power pins of the connector having the highest current flow and power pins of the connector having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used. Thicker power planes within the motherboard (as well as within the module) reduce the effective resistance per square of the power plane, and help distribute the current more uniformly to a greater number of power pins of the connector. The use of multiple power planes in parallel also achieves a lower effective resistance. Multiple power terminals connecting the source of regulated power supply voltage (or reference voltage, such as ground) to the power plane may be used instead of just one power terminal. Moreover, placing a pair of power terminals symmetrically about a line perpendicular to the connector which bisects the power pins of the connector helps distribute the current flow through the power plane to the power pins. By placing the power terminal (or terminals) at least a certain distance from the connector (e.g., at least 15 mm), a more uniform current flow through the connector is achieved.

Arrangement for reducing non-uniformity in current flow through various power pins within a printed wiring board connector for a removable module

An integrated circuit chip configuration, e.g., a microprocessor, includes feedback control circuitry defined thereon to control mid-frequency components of current demand of the integrated circuit chip and thereby regulate power supply voltage to within design tolerances of the integrated circuit chip. Such mid-frequency components can be generated by directed changes in operating frequency of the integrated circuit chip or by cyclic or episodic variations in circuit activity, e.g., instruction sequence dependent variations. When generated, such mid-frequency components can excite mid-frequency resonances in a power distribution system and generate power supply voltage disturbances. In some configurations, the integrated circuit chip includes current dump circuitry defining a controlled impedance path between first and second power supply voltage terminals of the integrated circuit chip. The controlled impedance path allows the feedback control circuitry to actuate a variable current draw so as to reduce mid-frequency components of overall current demand of the integrated circuit chip and thereby regulate power supply voltage disturbances. In other configurations, the feedback control circuitry is coupled to on-chip clock circuits, e.g., a phase-locked loop (PLL), to actuate variations in a clock signal supplied to the integrated circuit chip and thereby regulate power supply voltage disturbances.

Power surge management for high performance integrated circuit

A heat transfer apparatus is presented accommodating elevational disparity of an upper surface of a semiconductor device with respect to the component side of a PCB without adversely affecting system reliability. The heat transfer apparatus includes a thermally conductive cap structure positioned between the semiconductor device and an ambient and thermally coupled to the semiconductor device. One embodiment includes one or more spacers which maintain a space between the cap structure and the semiconductor device. A chip mounted to the substrate of a ceramic BGA package is mechanically isolated from the cap structure by the spacers, preventing chip damage due to shock and vibration. A backing plate on a side of the PCB opposite the semiconductor device provides PCB structural support and additional heat transfer. Several fasteners attach the backing plate to the cap structure. A portion of the fasteners exert a force which urges the cap structure toward the semiconductor device, while the remainder of the fasteners fix the relative positions of the backing plate and the cap structure. Fixing the relative positions of the backing plate and the cap structure reduces creep problems and promotes stress relief in viscoplastic elements. A first thermal interface layer between the cap structure and the semiconductor device achieves an acceptably low thermal resistance value under a relatively small amount of pressure. The spacers are omitted in an alternate embodiment wherein the first thermal interface layer has a uniform thickness and a consistency which permits the thickness to be maintained during installation.

Heat transfer apparatus which accommodates elevational disparity across

A low-profile heat transfer apparatus is presented for a surface-mounted semiconductor device employing a ball grid array (BGA) device package having a chip mounted upon a substantially flat upper surface of a substrate. The semiconductor device is mounted upon a component side of a printed circuit board (PCB), and the heat transfer apparatus is used to transfer heat energy from the semiconductor device to an ambient. A thermally conductive cap structure is positioned between the semiconductor device and the ambient. The cap structure includes a bottom surface having a first cavity sized to receive the substrate and possibly any decoupling capacitors. During use, the substrate resides within the first cavity. In a first embodiment, the chip resides within a second cavity in an upper wall of the first cavity during use. The chip and substrate are thermally coupled to the cap structure by a first and second thermal interface layer, respectively. The use of two thermal interface layers achieves a relatively low value of .theta..sub.JS, allowing the cap structure to remain relatively small. In a second embodiment, the chip resides within a hole in the cap structure during use such that the upper surface of the chip is exposed to the ambient. The substrate is thermally coupled to the cap structure by a thermal interface layer. The achieved value of .theta..sub.JS is acceptably low for some applications, and the height of the cap structure relative to the component side of the PCB is substantially reduced.

Low-profile heat transfer apparatus for a surface-mounted semiconductor

A method of providing a thermally conductive connection between spaced surfaces includes (a) mixing a thermally conductive filler containing a liquid metal into an unhardened matrix material, and (b) contacting the unhardened matrix material and randomly dispersed, separate spaced non-solidified regions of filler within the unhardened matrix material to the surfaces. A solid mechanical bond may be provided by hardening the matrix material or by providing a separate adhesive between the surfaces. Preferably, the regions of filler form separate spaced continuous thermally and electrically conductive paths between the surfaces.

Thermally conductive connection with matrix material and randomly

A process for making thermosetting or thermoplastic encapsulated integrated circuit having a heat exchanger in which one end of the heat exchanger is encapsulated in the housing adjacent to the integrated circuit and the other end is exposed to the environment beyond the housing portion. The process of making includes molding a heat exchanger into a thermosetting or thermoplastic package utilizing a preformed heat exchanger having a dissolvable or removable material which serves as a seal block during the molding operation. A plurality of thermally conductive heat exchanger elements are provided for providing the desired thermal performance while reducing the thermal stresses in the package.

Method for encapsulating an integrated circuit using a removable

The present invention discloses a thermally and electrically conductive adhesive material comprising a hardened adhesive, and a non-solidified filler containing a liquid metal dispersed in separate spaced regions of the adhesive. The hardened adhesive provides a mechanical bond whereas the filler provides continuous thermal and electrical metal bridges, each bridge extending through the adhesive and contacting the bonded surfaces. The method includes (a) dispersing a filler containing a liquid metal into an unhardened adhesive, (b) contacting the unhardened adhesive and the filler in non-solidified state to the surfaces resulting in separate spaced regions of the non-solidified filler contacting both surfaces, and (c) hardening the adhesive.

Thermally and electrically conductive adhesive material and method of

An encapsulated integrated circuit package having an integrated circuit chip with a plurality of electrical leads connected thereto and at least one thermally conductive screen mesh positioned adjacent to the chip. A non-electrically conductive thermosetting or thermoplastic material forms a housing enclosing the chip and bonded to the screen mesh. Preferably one of the layers is exposed to the outside of the housing and the screen mesh is secured to a substrate supporting the chip.

Growing community of inventors

Austin, TX, United States of America

Thomas P Dolbear