International Business Machines Corporation

International Business Corporation

Thomas P Comino

David Brian Stone

Ross William Keesler

Timothy W Budell

Steven G Rosser

Todd W Davies

David Peter Pagnani

Richard M Schroedl

Richard Gregory Bednar

Donald J Malling

A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.

Vents with signal image for signal return path

Chip carrier topology including a plurality of bond lines radiating from a line of chip pads to at least one of zero or more finger lines and zero or more voltage lines is defined by first collecting topology parameters selected from the set including the number of rows of fingers; the spacing between rows of fingers; finger style, said finger style being one of arc-of-circle, constant-bond-length, and encompassing-rectangle; location of voltage rings; value of voltage rings; location of chip pads; voltage of chip pads; dimensions of output fingers; minimum finger pair spacing; maximum finger angle with respect to its bond line; minimum spacing of bond line terminations at voltage rings; and minimum spacing of bond line terminations with respect to and adjacent bond line which terminates at a finger. A plurality of possible topology solutions are generated, and a single possible topology solution selected for further processing. From the single possible solution, a topology solution is generated by placing a middle finger with respect to a middle chip pad, processing alternative chip pads to the right and left sequentially from the middle chip pad selectively to position ring intercepts, inner row fingers and outer row fingers. The topology solution thus generated is evaluated and if acceptable, the result is output to an output file; if not acceptable for failure to conform to all topology parameters, the topology parameters are adjusted and the topology solution generated anew.

System and method for generating wire bond fingers

The positioning of mesh side features in a stencil mask are controlled to produce a mask which possesses high structural integrity and which exhibits a low service life. Mesh side feature control also eliminates certain unnecessary design side channels and mesh side via openings. Mesh side feature placement at T-shaped design side junctions is also controlled to produce a more uniform distribution of material which is screened through the stencil mask.

Stencil mask with channels including depressions

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Vestal, NY, United States of America

Thomas P Comino