International Telesystems Corporation

Thomas Ouellette

James J Frimmel, Jr

Richard N Deglin

John Ramsay

Lester A Potter

An apparatus for alternate memory addressing of a random access memory (RAM) allows a first processor to write into the memory on a row-by-row basis and a second processor to read out of the memory on a column-by-column basis. The memory is typically divided into a pluralilty of channels into which the first processor writes data for respective channels asynchronously by the use of twin RAMs. While one RAM is written to by the first processor, the second RAM is read from synchronously with automatic address translation.

Alternate memory addressing for information storage and retrieval

A solid-state telephone trunk interface circuit provides high isolation between a central office and telephone equipment. Opto-isolator transistors and a transformer are used to isolate the central office and the local equipment portions of the circuit. A switching transistor (Q4) is connected between a ring connector (3) and turned on and off via an opto-isolator transistor connected to a control connector (9). A ring detector (11) comprising a first diode bridge is connected between tip and ring connectors (2 and 3) via an opto-isolator transistor to a ring signal connector (13). First and second parallel and opposite sign line condition detectors are respectively connected between tip and ring connectors and via opto-isolator transistors to battery-reverse and battery-forward signal connectors (19 and 17). The voice circuit includes a second diode bridge connecting tip and ring connectors to a first winding of a transformer (T1). The circuit between the diode bridge and the first winding is completed by a high voltage transistor (Q3) which is turned on and off via an opto-isolator transistor connected to an off-hook connector ( 21). A second winding of the transformer is connected to first and second operational amplifiers respectively connected to voice signal input and output connectors (23 and 25). A feedback cancelling circuit is connected between the voice signal input connector and the input of the second operational amplifier for cancelling a portion of the voice signal input to the voice signal output.

Telephone trunk interface circuit

A digital voice recording and reproducing device, preferably connected to a telephone network uses a storage RAM to store voice messages and digital signals. An internal processor connected to the storage RAM processes digital signals to and from the storage RAM. A high speed RAM connected to the internal processor receives and transmits digital signals to and from the internal processor. Encoders and decoders encode voice signals into pulse code modulated (PCM) signals to be delivered into the high speed RAM, and decode digital PCM signals from the high speed RAM. A high speed processor (HSP) connected to the high speed RAM delivers signals from a switch to the high speed RAM. An internal processor connected to the switch, high speed RAM (HSP) and the storage RAM controls the input of signals to the high speed processor, to the high speed RAM and to the storage RAM, and controls the output of signals from the storage RAM to the internal processor and the high speed RAM, and then via the switch and the decoders to output means such as telephone lines.

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Fairfax Station, VA, United States of America

Thomas Ouellette