Intel Corporation

Infineon Technologies Ag

Intel IP Corporation

Thomas Ort

Bernd Waidhas

Thomas Wagner

Lizabeth Keser

Andreas Wolter

Andreas Augustin

Thorsten Meyer

Gottfried Beer

Georg Seidemann

Christian Geissler

Reinhard Mahnkopf

Sonja Koller

Klaus Pressel

Saravana Maruthamuthu

Veronica Sciriha

A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

Fan out package with integrated peripheral devices and methods

A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

Package formation methods including coupling a molded routing layer to an integrated routing layer

A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

Semiconductor packages, and methods for forming semiconductor packages

Fan out package and methods

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

Face-up fan-out electronic package with passive components using a support

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

Component magnetic shielding for microelectronic devices

An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

Molded substrate package in fan-out wafer level package

Package including an integrated routing layer and a molded routing layer

A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

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Veitsbronn, Germany

Thomas Ort