Skyworks Solutions, Inc.

Intel Corporation

Thomas Obkircher

Bipul Agarwal

Guillaume Alexandre Blin

William John Domino

Bang Li Liang

Adrian John Bergsma

Peter Harris Robert Popplewell

Peihua Ye

Yong Hee Lee

Jaleh Komaili

Yang Liu

John E Vasa

Wei-Hong Chen

Tom Taoufik Bourdi

Chandra Mohan

Nuttapong Srirattana

Bo Zhou

James Henry Ross

Bryan J Roll

Gregory Edward Babcock

Patrick Marcus Naraine

Stephane Richard Marie Wloczysiak

Junhyung Lee

Joshua Haeseok Cho

Rimal Deep Singh

Ardeshir Namdar-Mehdiabadi

Zijiang Yang

Yi Yang

Georgi Milev Taskov

Jaleh Komalil

A radio-frequency module has radio-frequency input and outputs and a radio-frequency core connected between them and configured to transition between operational states. An energy management core triggers a selected transition between two of the operational states via a sequence of transitions between the plurality of operational states.

Hot switching spur suppression

Radio frequency (RF) front ends with integrated channel matching calibration are provided herein. In one aspect, a front end system includes: a plurality of front end amplification chains including transmit and receive chains for at least two radio frequency bands, each of the front end amplification chains configured to either transmit or receive radio frequency signals via one of a plurality of antennas, and each of the front end amplification chains includes an amplifier configured to receive a bias current and amplify the corresponding radio frequency signal based on the bias current, a control circuit configured to generate each of the bias currents, and a multiplexor configured to receive the bias currents and provide the bias currents to the corresponding amplifiers.

Radio frequency front end with integrated channel matching calibration

A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.

Flip-chip semiconductor-on-insulator transistor layout

In some embodiments, a semiconductor chip device can include a semiconductor substrate having a switching circuit with a first node, and a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node. The plurality of layers can include a redistribution layer, and a signal path can be implemented as a part of the redistribution layer. The signal path can have a first end electrically connected to the first node and a second end electrically connected to the second node, and be configured to provide a selected inductance.

Radio-frequency switch having redistribution layer inductance

Bias schemes for cascode power amplifiers are disclosed. In certain embodiments, a power amplifier system includes a cascode power amplifier biased by a first cascode bias voltage and that amplifies a radio frequency input signal. The power amplifier system further includes a bias voltage generation circuit including a first switch, a first cascode transmit mode bias circuit that provides the first cascode bias voltage to the cascode power amplifier through the first switch in a normal power transmit mode, a low power mode bias circuit that overrides the first cascode transmit mode bias circuit to set the first cascode bias voltage in a low power transmit mode, a second switch, and a sleep mode bias circuit that provides the first cascode bias voltage to the cascode power amplifier through the second switch in a sleep mode.

Biasing of cascode power amplifiers for multiple operating modes

A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.

Power amplifier output matching

Programmable voltage regulators for powering multiple circuit blocks are disclosed. In certain embodiments, a front end system includes a plurality of circuit blocks, and a programmable low dropout regulator that generates a programmable regulated voltage for the plurality of circuit blocks based on a first multi-bit control signal. The programmable low dropout regulator includes a controllable frequency compensation circuit controlled by a second multi-bit control signal and operable to control a phase margin of the programmable low dropout regulator, and an overshoot control circuit controlled by a third multi-bit control signal and operable to control an overshoot of the programmable regulated voltage.

Programmable voltage regulators for powering multiple circuit blocks

Bias schemes for cascode power amplifiers are disclosed. In certain embodiments, a power amplifier system includes a cascode power amplifier powered by a first supply voltage and that amplifies a radio frequency input signal, and a bias circuit including a voltage regulator that generates a regulated voltage and is powered by the first supply voltage. The bias circuit further includes a bias voltage generation circuit that receives the regulated voltage and generates at least one cascode bias voltage for the cascode power amplifier, a switch that gates a second supply voltage to generate a gated supply voltage, a bias current generation circuit that controls a bias current of the cascode power amplifier and is powered by the gated supply voltage, and a gating circuit that controls the switch based on the regulated voltage and the second supply voltage.

Biasing of cascode power amplifiers for multiple power supply domains

Voltage regulation schemes for powering multiple circuit blocks are disclosed. In certain embodiments, a front end system includes a reference voltage circuit that receives power from a power supply voltage and generates a reference voltage, a group of circuit blocks each selectively enabled by a corresponding one of a group of enable signals, and a programmable voltage regulator that generates a programmable regulated voltage based on the reference voltage and provides the programmable regulated voltage to the circuit blocks. The programmable regulated voltage has a voltage level that changes based on a selection of the circuit blocks that are enabled by the enable signals.

Voltage regulation schemes for powering multiple circuit blocks

Cascode power amplifier bias circuits suitable for operating across multiple power supply domains are provided. In certain embodiments, a power amplifier system includes a cascode power amplifier and a multi-domain bias circuit that generates at least a first cascode bias voltage for the cascode power amplifier. The multi-domain bias circuit includes a coarse regulator that generates a regulated voltage based on a power supply voltage that is operable with multiple voltage levels associated with different power supply domains, a bandgap reference circuit that is powered by the regulated voltage and outputs a bandgap reference voltage, a bias voltage generator that generates multiple selectable bias voltages based on the bandgap reference voltage, and a bias voltage selector that chooses the first cascode bias voltage from amongst the selectable bias voltages.

A semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die includes at least one contact pad and a transistor including a first terminal formed within the active layer. A conduction path can include a plurality of first conduction path portions extending between the first terminal and the at least one contact pad and residing within a footprint of the at least one contact pad.

Semiconductor-on-insulator transistor layout for radio frequency power amplifiers

Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.

Growing community of inventors

Santa Ana, CA, United States of America

Thomas Obkircher