Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Nortel Networks Corporation

Avaya Inc.

Bull Nh Information Systems, Inc.

Eagleview, Inc.

Thomas O Holtey

Gary J Goss

Thomas L Murray, Jr

Thomas F Joyce

Steven S Noyes

Richard P Kelly

Kin C Yu

Robert C Miller

Kenneth E Bruce

James W Stonier

James C Raymond

James C Siwik

Scott W Smith

Wayne A Perzan

Victor Firoiu

Thomas S Hirsch

William Panepinto, Jr

J Nathaniel Marshall

Robert G Moles

Eric Haversat

Randall D Hinrichs

Daniel G Peters

Jian-Kuo Shen

John J Bradley

Ming T Miu

Peter Jeremy Wilson

Theodore R Staplin, Jr

Gregory Edward Lund

Frank V Cassarino, Jr

Xiaohui Zhang

Douglas L Riikonen

John D Borgman

Bardwell C Salmon

Ripeness indicators are provided and associated with statistics counters to enable the counters to be read once sufficient data has accumulated in the counters. The ripeness indicators may be used to signal to the network device when one or more counters has met or exceeded a predetermined value, such as 50%. Monitoring ripeness indicators associated with the counters enables the network device to harvest counters when they are sufficiently full to gather meaningful statistics from the counters, while ignoring counters that do not contain sufficient data or are not in danger of overflowing. This enables the network device to devote less resources to statistics gathering since high volume counters may be harvested more frequently than low volume counters. The ripeness indicators may be provided with individual counters, groups of counters, or accounts containing individual and/or groups of counters.

Method and apparatus for selectively reading counter information in a network device

A Balanced Packet Transmit Opportunity (BPTO) mechanism allows balanced bandwidth traffic to be serviced while still maintaining the service levels desired for high priority traffic. The above embodiment achieved the result by distinguishing both queue types and slot style types, and performing selections differently depending upon the relative styles of the queues and slots. This arrangement provides a number of advantages. Because the selection method is fast and relatively simple to implement, a large number of queues may be integrated into the decision process while maintaining a desired output bandwidth. In addition, the selection process provides a flexibility, allowing multiple traffic shaping considerations to be modified during operations to support changing network requirements. In addition, the selection process provides a flexibility, allowing multiple traffic shaping considerations to be modified during operations to support changing network requirements.

Queue scheduling with priority and weight sharing

A feedback output queuing system, apparatus, and method controls the rate at which packets are forwarded from the ingress ports to a particular output queue over the switching/routing fabric based upon the level of congestion at the output queue. The output queue is monitored and the level of congestion at the output queue is determined based upon a predetermined congestion determination mechanism. An ingress forwarding scheme is determined based upon the level of congestion at the output queue. Information is forwarded from the ingress ports to the output queue based upon the ingress forwarding scheme.

Feedback output queuing system, apparatus, and method

A computer-implemented system for brokering transactions between sellers and a buyer of goods or services, including a database, a seller interface, and a buyer's interface. The database contains information, including multimedia information, descriptive of respective ones of the goods or services. The seller interface enables the sellers to interactively enter information, including multimedia information, into the database. The buyer's interface provides a knowledge-based interactive protocol, enabling the buyer to select and review the descriptive information from the database, and makes perceptible the multimedia information in response to an interactive buyer request.

Computer-assisted system for interactively brokering goods or services

An application memory card system includes a secure memory card which can be operatively connected to communicate with a host mainframe microprocessor or hand held device host microprocessor via a standard interface. The secure memory card contains an application processor and an access control microprocessor (ACP), each of which connect through an internal bus to a number of non-volatile addressable memory chips, each organized into a plurality of blocks. Each microprocessor has an additional control signal line included in a control bus portion of its bus for specifying 'Execute' access. An access discrimination logic unit which connects to the internal bus and to the non-volatile memory includes an access by type memory writable by the application processor under the control of the ACP for maintaining security. The access discrimination logic unit combines the 'Execute' control access signal from a microprocessor with a signal designating the microprocessor source (e.g. external or internal) to define the type of memory access requested and transfers a control enabling signal as a function of the state of the selected stored access control bit indicating if the requested access is allowed to the addressed block.

Secure application card for sharing application data and procedures

A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values and program instruction information. Each chip's memory is organized into a number of blocks, each block including a number of rows of byte locations. Each row of each block further includes a lock bit location, the total number of which provide storage for a lock value uniquely coded to utilize a predetermined characteristic of the memory to ensure data protection. Each memory chip is constructed to include security control logic circuits which include a security access control unit and a volatile access control memory containing a plurality of access control storage elements. Under the control of a predetermined set of instructions, the security access control unit performs a predetermined key validation operation by comparing key values against the bit contents of lock bit locations read out a bit at a time during an authentication procedure with a host computer. After the successful performance of the key validation procedure, the microprocessor sets one of the storage elements of the volatile access control memory for enabling user access to block data.

Secure memory card with programmed controlled security access control

A secure memory card includes a microprocessor on a single semiconductor chip and one or more non-volatile addressable memory chips. The microprocessor chip and non-volatile memory chips connect in common to an internal card bus for transmitting address, data and control information to such non-volatile memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values, application specific configuration information and program instruction information. Each chip's memory is organized into a number of blocks or banks and each memory chip is constructed to include security control logic circuits. These circuits include a number of non-volatile and volatile memory devices which are loaded with key and configuration information under the control of the microprocessor only after the microprocessor has determined that the user has successfully performed a predetermined authentication procedure with a host computer. Thereafter, the user is allowed to read out information from blocks only as defined by the configuration information.

Secure memory card

A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.

Dual microprocessor control system

A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor. The processor, in response to the group of instructions, performs a designated operation for the line and in particular in response to the test instruction loads a new value corresponding to the starting instruction of the group of instructions of the next state.

Firmware state apparatus for controlling sequencing of processing

A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status.

Communications controller interface

A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

Facility for passing data used by one operating system to a replacement

A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

Pattern generation for a graphics display

The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and an attribute memory for storing display characteristics such as inverse video and blinking. The contents of the bit map and attribute memories and the output of the character generator are used to address a pre-programmed ROM. The output from the ROM is a string of three bit words with each bit stream representing a primary color on a color CRT and being connected to the associated color input to the CRT. Composite graphics and text are displayed on the CRT.

Computer display system for producing color text and graphics

A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

Microcomputer system with independent operating systems

A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.

Growing community of inventors

Newton, MA, United States of America

Thomas O Holtey