International Business Machines Corporation

Lockheed Martin Corporation

Thomas Norman Barker

James Warren Dieffenderfer

Peter Michael Kogge

Michael C Dapp

Vincent John Smoral

Donald Michael Lesmeister

David B Rolfe

Billy J Knowles

Clive Allan Collins

Richard Edward Nier

Paul Amba Wilkinson

Robert Reist Richardson

Eric Eugene Retter

Richard Ernest Miles

Nicholas Jerome Schoonover

James Robert Stupp

Howard Thomas Olnowich

Donald George Grice

David Christopher Kuchinski

Donald G Grice

Philip Heidelberger

Peter Anthony Franaszek

Nenad Rijavec

Bharat D Rathi

Gilbert C Vandling

Anujan Mangala Varma

Aubrey B Poore, Jr

Joseph A Persichetti

Gilbert Clyde Vandling, Iii

David Christoper Kuchinski

Priority inheritance is implemented across a distributed system, preferably by use of a mutual exclusion object, referred to as a pseudo-mutex, which provides operations for communicating priority of a task which is held to a different connected processor or node of a network and generating a dummy local command of priority at least equal to that of the held task at the remote processor or node in collaboration with a real-time operating system and middleware. The remote real time operating system then carries out priority inheritance in the normal manner to raise the priority of a blocked task, thus reversing any preemption of that task at the remote processor or node. The increase in priority avoids preemption of lower priority processes and thus increases the execution speed of the executing thread to release the existing lock at an earlier time; allowing a lock to be obtained by the higher priority thread. The middleware serves as an intermediary, communicating messages that include pseudo-mutex arguments or similar communications and requests for enabling priority inheritance across nodes.

System and method for implementing distributed priority inheritance

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Fully distributed processing memory element

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.

Picket autonomy on a SIMD machine

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a 'cluster ring'. Corresponding nodes of eight cluster rings are connected into rings in the W dimension.

N-dimensional modified hypercube

A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.

Controller for a SIMD/MIMD array having an instruction sequencer

In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to 'slide' through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.

Slide network for an array processor

A dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously. The apparatus permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. The apparatus permits multiple multi-cast operations to occur simultaneously within the network. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate among themselves without involving other nodes that are not in its own subset. Hardware circuitry detects and corrects deadlock conditions in the multi-stage network. The hardware circuitry detects all the different types of deadlock conditions automatically and issues correction indications to the network paths involved. The network deadlock is thereby eliminated, and the two broadcasts or multi-casts involved continue their operation in a rearranged sequence that will not cause deadlock.

Priority broadcast and multi-cast for unbuffered multi-stage networks

A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.

Multi-function network

SIMD/MIMD processing memory element (PME)

A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.

Advanced parallel array processor I/O connection

Advanced parallel array processor(APAP)

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Advanced parallel processor including advanced support hardware

Growing community of inventors

Vestal, NY, United States of America

Thomas Norman Barker