Infineon Technologies Ag

Qimonda North America Corporation

Qimonda Ag

International Business Machines Corporation

Macronix International Co., Ltd.

Other

Infineon Technologies North America Corp.

Thomas Nirschl

Jan Otterstedt

Thomas Happ

Wolf Allers

Michael Bollu

Jan Boris Philipp

Ronald Kakoschke

Berndt Gammel

Doris Schmitt-Landsiedel

Gerd Dirscherl

Philip Schlazer

Thomas Kern

Martin Ostermayr

Ulrich Backhausen

Jens Rosenbusch

Michael Bernhard Sommer

Christian Pacha

Christian Peters

Stefan Rueping

Stephan Henzler

Thomas Schulz

Mark C Lamorey

Georg Georgakos

Danny Shum

Klaus Schruefer

Yannick Martelloni

Juergen Holz

Edvin Paparisto

Jörg Berthold

Klaus Schrüfer

David Mueller

Alexander Olbrich

Philipp Hofter

Hsiang-Lan Lung

Ming-Hsiu Lee

Dominique Savignac

Roger W Cheek

Nigel Chan

Bernhard Wicht

Mayk Roehrich

Peter Huber

Thomas Liebermann

Klaus Aufinger

Christoph Bukethal

Matthias Schobinger

Alexander Duch

Christoph Roll

Xiangting Bi

Heinz Hönigschmid

A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.

Systems and methods utilizing a flexible read reference for a dynamic read window

The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

System and method to emulate an electrically erasable programmable read-only memory

The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

System and method for emulating an EEPROM in a non-volatile memory device

An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Integrated circuit and method for manufacturing the same

A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.

Word line address scan

Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Current sense amplifier with replica bias scheme

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.

Operation scheme for non-volatile memory

A circuit arrangement comprising a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and second access lines, the second access lines comprising at least two bit-lines; an access controller controlling access to at least one of the electronic components via the at least one first access line and the second access lines; and a first group of switches, wherein each switch comprises at least one control terminal and at least two controlled terminals. Each switch of the first group is connected to one of the at least two bit-lines via its control terminal and in a path between one first access line and a sense amplifier via its controlled terminals, and adjacent switches are connected via their control terminals to different bit-lines of the at least two bit-lines.

Circuit arrangement and method for operating a circuit arrangement

One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

Electronic device with a programmable resistive element and a method for blocking a device

A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of the plurality of first access lines other than the selected first access line and the one or two first access lines arranged adjacent to the selected first access line are floating.

A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.

Memory and method for programming memory cells

One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

Method of operating phase-change memory

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD) in comparison with other transistors (T) on the same integrated circuit arrangement (). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D, S) of the tunnel field effect transistor.

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Essex Junction, VT, United States of America

Thomas Nirschl