Infineon Technologies Ag

Siemens Aktiengesellschaft

Inmos Limited

Advanced Risc Machines Limited

Philips Electronics N.v.

Matra Mhs S.a.

Thomas Niedermeier

Tim Schoenauer

David Walter Flynn

Andrew Michael Jones

Michael Kund

Georg Georgakos

Joerg Berthold

Siegmar Koeppe

Bruno Douady

Peter Klapproth

Peter Rohm

Jacobus Christophorus Koot

Frederik Zandveld

James Graham Matthew

Richard Schmid

A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.

Memory element, memory read-out element and memory cell

The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.

Multi-context memory cell

The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be connected to the master latch for the purpose of buffer storing the data bit; at least one second slave latch which can be connected to the master latch for the purpose of buffer storing the data bit, and having an evaluation logic unit which outputs the configuration bit on the basis of the data bits which are buffer stored in the master latch and in the slave latches. In addition, the invention provides a shift register for safely providing configuration bits which has a plurality of inventive shift register cells which are connected in series to form a shift register chain.

Shift register for safely providing a configuration bit

A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.

Method for operation of a bus system for highly flexible and quick data

Growing community of inventors

Rosenheim, Germany

Thomas Niedermeier