Semiconductor Components Industries, LLC

Thomas Neyer

Kyeongseok Park

Michael John Seddon

Bongyong Lee

Fredrik Allerstam

Doojin Choi

Kevin Kyuheon Cho

Andrei Konstantinov

Wai Lun Chu

James Joseph Victory

Thierry Bordignon

Stanley Benczkowski

YunPeng Xiao

Vaclav Valenta

Mehrdad Baghaie Yazdi

Christopher Lawrence Rexer

Hyeongwoo Jang

Peter Dingenen

Roman Sickaruk

Ki Min Kim

Hao Wang

Jaume Roig-Guitart

Martin Domeij

Xiaoli Wu

Herbert De Vleeschouwer

Tirthajyoti Sarkar

Thi Thu Phuong Pham

Sungkyu Song

Hocheol Jang

Bohee Kang

Xiang Zeng

Jangkwon Lim

Jeongwoo Yang

A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

Power device with graded channel

A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

MOSFET device with undulating channel

Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Systems and methods for designing a discrete device product

In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.

Termination structures with reduced dynamic output capacitance loss

In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.

Vertical transistors with gate connection grid

A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.

Power device including metal layer

Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.

Semiconductor substrate singulation systems and related methods

Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.

Semiconductor wafer thinning systems and related methods

A diode with a current sensor is disclosed. The diode includes an anode region, a cathode region, and a channel-stop region. The diode further includes a sense resistor that is connected between the channel-stop region and the cathode region. When the diode is forward biased, a sense current flows through the sense resistor that corresponds to the forward current flowing through the diode. When the diode is reverse biased, the channel-stop region helps prevent a breakdown condition in the diode.

Diode with current sensor

A semiconductor power device may include a Silicon Carbide (SiC) layer having an active power device formed on a first surface thereof. An Ohmic contact layer may be formed on a second, opposing surface of the SiC layer, the Ohmic contact layer including Nickel Silicide (NiSix) with a first silicide region containing a first precipitate of non-reacted carbon disposed between the SiC layer and a second silicide region. The second silicide region may be disposed between the first silicide region and a third silicide region, and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of non-reacted carbon. The third silicide region may contain a second precipitate of refractory metal carbide. A solder metal layer may be formed on the Ohmic contact layer, with the third silicide region disposed between the second silicide region and the solder metal layer.

Carbon-controlled ohmic contact layer for backside ohmic contact on a silicon carbide power semiconductor device

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Munich, Germany

Thomas Neyer