Zenith Data Systems Corporation

Zenith Electronics Corporation

Thomas N Robinson

Anthony M Olson

Babu Rajaram

Todd R Witkowski

Mark D Nicol

Jimmy Dean Smith

A computer system includes a system bus having a plurality of address lines and having a first control line. A connector is coupled to the address lines and the first control line, and can removably receive a circuit card which can accept and/or generate signals on the address lines and first control line. A bus control circuit is coupled to the address lines and to a second control line, and can accept and/or generate signals on the address lines and second control line. A signal blocking circuit is coupled to both of the control lines and to the address lines, responds to the occurrence of a control signal on the second control line by respectively effecting and inhibiting application of the control signal to the first control line when the address on the address lines is respectively within and outside a predetermined group of addresses, and responds to the occurrence of the control signal on the first control line by applying the control signal to the second control line regardless of the address on the address lines.

Method and apparatus to disable ISA devices for EISA addresses outside

A computer system includes a control circuit having a request input, and a pair of connectors which are electrically coupled to the control circuit and are each connected to the request input of the control circuit, each connector being capable of removably receiving a circuit card. The control circuit includes a checking arrangement for detecting a condition in which the connectors each have therein a card having a request output controlling the request input of the control circuit.

Dual connector port for bus master card

A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle. In response to the acknowledge line and enable line being simultaneously actuated while the control line remains deactuated throughout a cycle, an arrangement supplies a special signal to the controller circuit so that the controller circuit interprets the cycle as a data transfer cycle and does not set a false error indication.

Floppy disk controller interface for suppressing false verify cycle

Page mode memory access is enabled despite an immediately previous idle cycle. A row address strobe signal is maintained active during an idle cycle so that if a page hit is detected on a subsequent memory cycle, all that is needed to read or write to memory is a column address strobe signal which can be provided via a page mode access. In this manner, memory speed is enhanced because a conventional access is not required on the first memory cycle following one or more idle cycles.

Method for improving the page hit ratio of a page mode main memory system

A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.

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St. Joseph, MI, United States of America

Thomas N Robinson