International Business Machines Corporation

Thomas N Jackson

Jerry M Woodall

Peter Daniel Kirchner

John Lawrence Freeouf

George D Pettit

Steven Lorenz Wright

Sandip Tiwari

Richard F Rutz

William H Price

Masanori Murakami

Devendra K Sadana

Terry I Chappell

Rodney T Hodgson

Hans S Rupprecht

Alan W Kleinsasser

Jeffrey Y Tang

Paul M Fahey

Steven E Laux

Craig M Ransom

James J Rosenberg

Gwen Pepper

Peter Oelhafen

Joseph F Degelormo

A method is provided for diffusion doping of semiconductor chips and wafers, in particular silicon chips and wafers, at peak concentrations of greater than about 3.times.10.sup.19 atoms/cm.sup.3. The semiconducting material to be doped is placed in a furnace wherein the furnace contains an atmosphere of a carrier gas and a dopant containing gas. The doping containing gas is greater than about 0.1 volume percent of the total volume in the furnace chamber. The pressure of the composite gas is greater than about 0.1 Torr. The composite gas has an oxidizing agent concentration of less than about 1 part per million. The method permits the direct doping of a silicon surface to form a shallow n-doped region having a high peak concentration by a diffusion process thereby eliminating damage to the silicon surface from ion implantation which is the commonly used method to achieve these high doping concentrations. Since the method is nondirectional trench sidewalls can be doped at high concentrations.

Highly doped semiconductor material and method of fabrication thereof

The control of barriers to carrier flow in a contact between a metal and a higher band gap semiconductor employing an intermediate lower band gap semiconductor with doping and greater than 1.5% lattice mismatch. A WSi metal contact of doped InAs on GaAs of 7.times.10.sup.-6 ohm/cm.sup.2 is provided.

Method for forming distributed barrier compound semiconductor contacts

A semiconductor device where an emitter material composition and doping profile produces an electron gas in a base adjacent a band offset heterojunction interface, the electrons in the electron gas in the base are confined under bias by a low barrier and the ballistic carriers have their kinetic energy controlled to prevent intervalley scattering by an electrostatic barrier that under influence of bias provides an essentially level conduction band in the portion of the base adjacent the collector.

Semiconductor ballistic electron velocity control structure

A vertical heterojunction equal area transistor and starting structure therefor is provided in which three epitaxial layers structure with wide band gap external layers and narrower band gap center layer is provided with peripheral impurity concentrations such that the area around the wide gap electrodes is high resistivity and the area around the center narrower gap region is high conductivity. A bipolar transistor of GaAs-Ge-GaAs is described.

Self-aligned heterojunction transistor

A low band gap semiconductor heterostructure having a surface adaptable to planar processing and all semiconductor properties supported by a fabrication constraint relaxing substrate that does not provide a low impedance parallel current path. A superconductor normal superconductor device of n-InAs-100 nanometers thick with niobium superconductor electrodes spaced 250 nanometers apart and a 100 nanometer gate in the space. The N-InAs is supported by an undoped GaAs layer on a semi-insulating GaAs substrate. A heterojunction field effect transistor device having a GaAlAs gate over a channel 100 nanometers thick on an undoped GaAs layer on a semi-insulating GaAs substrate.

Semiconductor heterostructure adapted for low temperature operation

In a semiconductor device, a contact with low resistance to a III-V compound semiconductor substrate was fabricated using refractory materials and small amounts of indium as the contact material. The contact material was formed by depositing Mo, Ge and W with small amounts of In onto doped GaAs wafers. The contact resistance less than 1.0 ohm millimeter was obtained after annealing at 800.degree. C. and the resistance did not increase after subsequent prolonged annealing at 400.degree. C.

Thermally stable low resistance contact

A layer of an amphoteric dopant on the surface of a group III-V intermetallic semiconductor crystal will diffuse into the crystal surface in a heating cycle forming a stable contact. The contact can be ohmic or rectifying depending on the localized presence of an excess of one crystal ingredient. A layer of Si on GaAs upon heating forms a rectifying contact. When the layer of Si contains As, the contact is ohmic.

Group III-V semiconductor electrical contact

Degradation of the cleaved light output surface of a semiconductor crystal injection laser is reduced through control of surface recombination by providing an annealed optically transparent coating at least one ingredient of which has a higher bandgap than said crystal over the cleaved light output surface. Crystals of GaAs, GaAlAs and GaInAsP are provided with annealed coatings of ZnS, CdS, CdTe and CdSe.

Semiconductor injection lasers

An electrical device which employs two-dimensional space charge modulation in a semiconductor structure. The device has an approximately Debye length wide contact and a rectifying contact positioned adjacent to each other within a Debye length on a semiconductor body and a contact remotely positioned. A bias on the rectifying contact will effect conduction between the other contacts.

Space charge modulation device

A method of manufacturing GaAs semiconductor devices includes the steps of emplacing doping impurities by ion implantation on at least one surface of a GaAs substrate, and a step of annealing to remove damage resulting from the implantation of the impurities in the GaAs material. Prior to the annealing, a silicon capping layer is deposited on the surface by either sputtering, evaporation, or vapor deposition to a thickness of 100-10,000 angstroms. Subsequent to the annealing, the silicon capping layer is removed by etching. The silicon cap prevents out-diffusion of arsenic from the GaAs, and has a coefficient of thermal expansion which is sufficiently close to that of the GaAs to inhibit the formation of cracks in the capping layer.

Silicon cap for annealing gallium arsenide

Crystalline compound semiconductors are passivated with a layer of the most volatile element thereof to prevent the formation of oxides that would interfere with further processing. A GaAs crystal is provided with a surface layer of arsenic. The arsenic layer is formed by exposure to light having a photon energy greater than 1.8 eV, at a power density of 0.01 to 0.5 watts per cm.sup.2 while the GaAs immersed in a 1:1 HCl:H.sub.2 O solution for a period of 10-30 minutes. The intermediate processing passivated GaAs crystal may be stored and handled in air and the As layer is removed by low temperature baking.

Intermediate passivation and cleaning of compound semiconductor surfaces

The edge of a conformal coating over a mesa is usable to define a shoulder in the vertical dimension of the mesa which in turn is used for positioning. Structures are provided that permit electrodes at precise locations along the length of a mesa. A vertical field effect transistor is set forth with a mesa serving as the channel and the gate electrode positioned at a shoulder formed by the edge dimension of a coating on the sides of the mesa.

Vertical MESFET with mesa step defining gate length

A 10.sup.-6 ohm cm.sup.2 ohmic contact is provided by formation of a 20-50 Angstroms deep surface region with a net donor density of higher than 5.times.10.sup.19 /cc. An amphoteric dopant of Si or Ge is incorporated in a pinned Fermi level condition so that an enhanced surface donor concentration occurs.

Intermetallic semiconductor ohmic contact

A quantity of silicon serving as a source of the element silicon for use in a molecular beam epitaxial growth apparatus where the silicon is in the form of a monocrystalline wafer with a plurality of electrically parallel filaments separated by slots that pass completely through the wafer, each filament having a length dimension that is greater than the width and height dimensions, joined at a broad contact area at each filament end and where an electric current is passed through the filaments through the broad contact areas.

Silicon source component for use in molecular beam epitaxial growth

A submicron conductor is formed by placing a metal member over an insulator both terminating at a common defined edge. An angularly deposited metal against the edge provides a broad metal conductor attached along the entire edge of a thin metal member which is positioned on the substrate on a narrow line with the width defined by the horizontal component of the angular deposition. A removal operation removes with respect to the vertical component of the angular deposition the excess angularly deposited metal and leaves a vertical, very narrow metal conductor having a horizontal metal over the dielectric in electrical and supporting contact along the entire length. The asymmetry of the conductor provides field effect transistor advantages.

Growing community of inventors

Peekskill, NY, United States of America

Thomas N Jackson