Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Thomas N Indermaur

Derek L Knee

John G McBride

Jonathan P Lotz

Peter David Maroni

Matthew L Biggio

William Weiner

James Kwok Yue Wai

A link module architecture is disclosed for use with a multi-core central processing unit having a cross bar switch. The link module comprises timing recovery circuitry operably coupled to the central processing unit, wherein the timing recovery circuitry is positioned proximate to the cross bar switch. The link module further comprises a bit receiver operably coupled to the central processing unit, and a bit output driver operably coupled to the central processing unit. The bit receiver, preferably comprising a wide bandwidth amplifier, and the bit driver are preferably integrated with a sea of on-chip RAM.

Distributed link module architecture

Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.

Hierarchical metal one usage tool for child level leaf cell

The present invention is generally directed to a system and method for evaluating a very large scale integrated circuit design in a structured, hierarchical fashion. In accordance with one aspect of the invention, a method evaluates a first circuit portion for a variety of potential errors and generates a first list of potential errors identified in the first circuit portion. The method further includes the step of adding at least one of the potential errors to a waiver file. The method further includes the step of examining a second circuit portion for a variety of potential errors, except those errors listed in the waiver file. In one embodiment, the step of examining the second circuit portion may be executed in a variety of ways. In one embodiment, the step may be configured to evaluate the second circuit portion for a number of potential errors. For any error(s) so identified, the method may add the errors to an error listing that is to be reported. However, the method may then exclude or omit from this listing any errors (or tests) listed in a waiver file. An associated system is also provided.

System and method for evaluating a very large scale integrated circuit for potential design errors

A method and structure of power balancing is capable of simultaneously minimizing maximum power while also reducing the step load of any electronic system, subsystem, or device having one or more functional units or resources that are not in constant use and that are therefore capable of being selectively powered-down or powered-up.

Growing community of inventors

Denver, CO, United States of America

Thomas N Indermaur