International Business Machines Corporation

Globalfoundries Inc.

State University of New York

University of Delaware

Infineon Technologies Ag

Globalfoundries U.S. 2 LLC

Matheson Tri-gas, Inc.

Thomas N Adam

Alexander Reznicek

Kangguo Cheng

Ali Khakifirooz

Bruce Bennett Doris

Raghavasimhan Sreenivasan

Stephen W Bedell

Devendra K Sadana

Judson Robert Holt

Ghavam G Shahidi

Keith E Fogel

Joel Pereira De Souza

Pouya Hashemi

Hong He

Douglas Duane Coolbaugh

Jinghong Li

Thomas A Wallner

Gerald L Leake

Tenko Yamashita

Shom Ponoth

Qizhi Liu

Rajendran Krishnasamy

Kathryn Turner Schonenberg

Eric C Harley

Eric C T Harley

James Kolodzey

Ruilong Xie

Juntao Li

Veeraraghavan S Basker

Theodorus E Standaert

Kevin K Chan

Davood Shahrjerdi

Xiuyu Cai

Alvin Jose Joseph

Chung-Hsun Lin

Marwan H Khater

Pranita Kulkarni

David Louis Harame

Paul Charles Jamison

Dennis W Prather

Ashima B Chakravarti

Keith Howard Tabakman

Anita Madan

Sebastian Naczas

Beth Ann Rainey

Balasubramanian Pranatharthi Haran

Teresa L Pinto

Ramachandra Divakaruni

Dureseti Chidambarrao

Balasubramanian Pranatharthiharan

Dominic Joseph Schepis

Amlan Majumdar

Conal Eugene Murray

Balasubramanian S Haran

Donald Francis Canaperi

Henry K Utomo

Abhishek Dube

Jin-Ping Han

Charan V Surisetty

Stefan Schmitz

Robert Torres, Jr

Charan Veera Venkata Satya Surisetty

O Sung Kwon

Matthew W Stoker

David C Ahlgren

Bala S Haran

Satoshi Hasaka

Paul D Brabant

Oh Jung Kwon

Terry Arthur Francis

Alexander Reznieck

Samit Kumar Ray

Pengcheng Lv

Ralph Thomas Troeger

Miron S Kagan

Irina N Yassievich

Maxim A Odnoblyudov

A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Integrated photonics including waveguiding material

Integrated photonics including germanium

A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication

A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

Field effect transistors with varying threshold voltages

A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

Semiconductor structure having a source and a drain with reverse facets

A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

FinFET having an epitaxially grown semiconductor on the fin in the channel region

A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure.

Formation of bulk SiGe fin with dielectric isolation by anodization

FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins.

Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition

A FinFET device includes a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins. At least one sidewall of each of the plurality of fins remain uncovered by the nitride material. The nitride material may also not contact the bottom of the plurality of fins.

A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region.

Semi-conductor device with epitaxial source/drain facetting provided at the gate edge

A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.

Bulk semiconductor fins with self-aligned shallow trench isolation structures

Integrated passive devices for silicon on insulator (SOI) FinFET technologies and methods of manufacture are disclosed. The method includes forming a passive device on a substrate on insulator material. The method further includes removing a portion of the insulator material to expose an underside surface of the substrate on insulator material. The method further includes forming material on the underside surface of the substrate on insulator material, thereby locally thickening the substrate on insulator material under the passive device.

Integrated passive devices for finFET technologies

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Poughkeepsie, NY, United States of America

Thomas N Adam