International Business Machines Corporation

Globalfoundries Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Other

Awemane Ltd.

Thomas Mittelholzer

Roy Daron Cideciyan

Charalampos Pozidis

Nikolaos Papandreou

Robert Allan Hutchins

Thomas P Parnell

Evangelos Stavros Eleftheriou

Sedat Oelcer

Keisuke Tanaka

Paul Joseph Seger

Tobias Blaettler

Richard Leo Galbraith

Charles John Camp

Ajay Dholakia

Travis Roger Oenning

Milos Stanisavljevic

Luis Alfonso Lastras-Montano

Michele M Franceschini

Katherine Tyldesley Blinick

Timothy J Fisher

Glen Alan Jaquette

Roman Alexander Pletka

John Peter Karidis

Hisato Matsuo

Mayank Sharma

Kenji Ohtani

Mario Blaum

Weldon Mark Hanson

Ibrahim M Elfadel

Sasa Tomic

Stefanie Ruth Chiras

David James Stanek

Nhan Xuan Bui

Andrew Dale Walls

Nikolas Ioannou

Matthew Joseph Breitwisch

Bruce Alexander Wilson

Kazuhiro Tsuruta

Mark N Wegman

Gary A Tressler

Roger W Cheek

Kubilay Atasu

Ksenija Lakovic

Giovanni Cherubini

Daniel Frank Moertl

Steven Robert Hetzler

Jens Jelitto

Aaron Daniel Fry

Robert Edward Galbraith

Ioannis Koltsidas

Robert Haas

Jonathan Darrel Coker

Robert Allen Hutchins

Alessandro Sorniotti

Damir Anthony Jamsek

Andrew Kenneth Martin

Michail Vlachos

Thomas J Griffin

Slavisa Sarafijanovic

Xiao-yu Hu

Theodore Antonakopoulos

Michael Joseph Ross

Haris Pozidis

Celestine Duenner

Mussie T Negussie

Rick Galbraith

Jon Coker

Ilias Iliadas

Jan Stanek

Robert Allen Hutchins, Iii

Weldon M Hanson

Travis R Oenning

Evangelos S Eleftheriou

Roy D Cideciyan

Richard L Galbraith

Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.

Dynamic mapping of logical to physical memory for increased performance

In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.

Partial reverse concatenation for data storage devices using composite codes

A memory system, Reed Solomon ('RS') Decoder, and method for decoding Reed-Solomon codewords includes: a Syndrome Computation engine configured as a first stage of a pipeline for receiving the RS codeword and computing one or more Syndromes; an initialization unit for providing initialization values for a key equation solver engine that generates the errata locator polynomial and the errata magnitude polynomial configured as a second stage; and as a third stage a Chien Search engine for receiving the error locator polynomial and determining the one or more locations of the one or more erasures and random errors in the received RS codeword and an error-value evaluation ('EE') engine for receiving the errata magnitude polynomial and determining the one or more magnitudes of the one or more erasures and random errors in the RS received codeword.

System and method for optimizing Reed-Solomon decoder for errors and erasures

The example embodiments of the invention notably are directed to a computer-implemented method for assessing distances between pairs of histograms. Each of the histograms is a representation of a digital object; said representation comprises bins associating weights to respective vectors. Such vectors represent respective features of said digital object. This method basically revolves around computing distances between pairs of histograms. That is, for each pair {p, q} of histograms p and q of said pairs of histograms, the method computes a distance between p and q of said each pair {p, q}. In more detail, said distance is computed according to a cost of moving p into q, so as to obtain a flow matrix F, whose matrix elements Findicate, for each pair {i,j} of bins of p and q, how much weight of a bin i of p has to flow to a bin j of q to move p into q. This is achieved by minimizing a quantity &#x3a3;F&#xb7;C, where Cis a matrix element of a cost matrix C representing said cost. Said quantity &#x3a3;F&#xb7;Cis minimized under two flow constraints, which, interestingly, include a relaxed flow constraint F&#x2264;r, in addition to a complementary flow constraint. The relaxed flow constraint F&#x2264;ris applied for at least some of the pairs {i,j}, with requal to por q, where pand qare weights associated to bins i and j of p and q, respectively, and the complementary flow constraint is either an out-flow constraint &#x3a3;F=pif r=qor an in-flow constraint &#x3a3;F=qif r=p. The invention is further directed to related computer program products.

Assessing distances between pairs of histograms based on relaxed flow constraints

A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.

Virtual to physical translation and media repair in storage class memory

A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm&#x2014;e.g., a first programming pass and a second programming pass&#x2014;for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.

Managing programming errors in NAND flash memory

A method for parallelizing a training of a model using a matrix-factorization-based collaborative filtering algorithm may be provided. The model can be used in a recommender system for a plurality of users and a plurality of items. The method includes providing a sparse training data matrix, selecting a number of user-item co-clusters, and building a user model data matrix by matrix factorization such that a computational load for executing the determining updated elements of the factorized sparse training data matrix is evenly distributed across the heterogeneous computing resources.

Load-balancing training of recommender system for heterogeneous systems

A technique for selecting context models (CMs) for a CM ensemble (CME) in a context mixing compressor includes measuring compression ratios (CRs) of the compressor on a dataset for each CM included in a base set of CMs. A first CM that has a maximum CR for the dataset is added to the CME. In response to a desired number of the CMs not being in the CME, subsequent CRs for the compressor are measured on the dataset for each of the CMs in the base set of CMs that are not in the CME in conjunction with one or more CMs in the CME. In response to a desired number of the CMs not being in the CME, subsequent CMs that in conjunction with the one or more CMs in the CME result in a maximum subsequent CR for the dataset are added to the CME.

Building a context model ensemble in a context mixing compressor

In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S' of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S&#x2032; in the data storage system with the prior set S.

Updating prefix codes for pseudo-dynamic data compression

In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The embodied program instructions are readable/executable by a processor to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code includes encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes. Other computer program products for writing data to a storage medium of a data storage system using a partial reverse concatenated modulation code are presented according to more embodiments.

Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Diagonal anti-diagonal memory structure

In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.

A data protection technique combines error correcting code and redundant array of independent disk functionality for a non-volatile memory (NVM) array of a data storage system. The technique includes receiving, by a controller, data for storage in the NVM. In response to receiving the data for storage in the NVM array, the controller forms first component codewords based on encodings with a first level code of respective first portions of the data. In response to receiving the data for storage in the NVM array, the controller forms a second component codeword based on an encoding with a second level code of a second portion of the data and the first component codes. The controller stores a respective portion of each of the first and second component codeswords on packages of the NVM array. The storing achieves maximum equal spreading of each of the component codewords across all of the packages.

Data protection techniques for a non-volatile memory array

A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.

Non-binary context mixing compressor/decompressor

A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.

Reducing a decoding error floor by post-processing codewords encoded by binary symmetry-invariant product codes

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Zurich, Switzerland

Thomas Mittelholzer