Oracle International Corporation

Thomas Mitchell

Mani Viswanath

Krishnan Sundaresan

Yibin Xia

John Eitrheim

Quan Tran

A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.

User-defined partitions for logical and physical circuit syntheses

A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-Synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells for the integrated circuit. The method may further include determining, using a cross-probe criterion, an amount of cross-correlation between a first cell and a second cell in the gate-level netlist. The method may further include generating, in response to the amount of cross-correlation exceeding a correlation threshold, a cell group including the first cell and the second cell. The method may further include determining a boundary condition for the cell group. The method may further include generating a floorplan. The first cell and the second cell may be placed in the floorplan according to the boundary condition.

Designing circuits using pseudohierarchy

A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.

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Austin, TX, United States of America

Thomas Mitchell