Infineon Technologies Ag

Qimonda Ag

Qimonda Flash Gmbh & Co. Kg

Qimonda Flash Gmbh

Thomas Mikolajick

Josef Willer

Nicolas Nagel

Walter Hartner

Rainer Bruchhaus

Gerhard Enders

Marcus Halik

Hagen Klauk

Christine Dehm

Corvin Liaw

Thomas Peter Haneder

Matthias Kr&ouml;nke

Michael R&ouml;hner

Thomas Kern

Günter Schmid

Matthias Goldbach

Hans Reisinger

Michael Specht

Christoph Ludwig

Dominik Olligs

Veronika Polei

Igor Kasko

Marcus Kastner

Torsten Mueller

Norbert Schulze

Jan-Malte Schley

Karl-Heinz Kuesters

Franz Hofmann

Albert Birner

Volker Weinrich

Thomas Hecht

Stefan Jakschik

Lars Bach

Matthias Kroenke

Matthias Krönke

G&uuml;nter Schmid

Michael Röhner

Karl Heinz Kuesters

A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Memory cell arrangements

Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Integrated circuits and methods of manufacturing thereof

A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Semiconductor memory having charge trapping memory cells and fabrication method thereof

An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

Measuring circuit and reading method for memory cells

An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.

Evaluation circuit and evaluation method for the assessment of memory cell states

A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional 'contact to interconnect' structures.

Method for forming a semiconductor product and semiconductor product

To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

Charge-trapping memory device and methods for operating and manufacturing the cell

A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

Memory cell arrays and methods for producing memory cell arrays

A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.

Method for fabricating a semiconductor memory cell

An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

Multi-bit virtual-ground NAND memory device

A memory cell patterned as a trench transistor is provided with a first gate electrode () as auxiliary gate for source-side injection and a second gate electrode () electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence () provided for charge trapping and comprising a storage layer () between boundary layers (). The first gate electrode () and the second gate electrode () are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (). Source/drain regions () are arranged on the top side laterally with respect to the trenches. Word lines (), source/drain lines and control gate lines are present for the electrical driving.

Charge trapping memory cell and fabrication method

Silicon nanocrystals are applied as storage layer () and removed using spacer elements () laterally with respect to the gate electrode (). By means of an implantation of dopant, source/drain regions () are fabricated in a self-aligned manner with respect to the storage layer (). The portions of the storage layer () are interrupted by the gate electrode () and the gate dielectric (), so that a central portion of the channel region () is not covered by the storage layer (). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

Method for fabricating a memory cell

Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

Charge-trapping memory device and method of production

A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

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Dresden, Germany

Thomas Mikolajick