Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Hgst, Inc.

Ovonyx Inc.

Contour Semiconductor, Inc.

Other

Thomas Michael Trent

Ward M Parkinson

James E O'Toole

Daniel Robert Shepard

Nathan Franklin

Mac D Apodaca

James Juen Hsu

Christopher John Petti

Michael Grobis

Michael Nicolas Albert Tran

Hans Jurgen Richter

James W Reiner

Sam Ira Young

Steven Jeffrey Grossman

Technology is disclosed for a current source for reading a memory cell having a threshold switching selector. The current source may be operated in a first mode when turning on the threshold switching selector and in a second mode when sensing a voltage across the memory cell. The first mode may allow the use of the full range of the power supply voltage, which provides sufficient voltage across the memory cell to turn on the threshold switching selector. In the second mode the magnitude of the read current is less dependent on the voltage across the memory cell. The second mode therefore provides for accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, which provides sufficient voltage across the memory cell to write the memory cell.

Current source for read of programmable resistance memory cells

Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.

Cross-point array IHOLD read margin improvement

A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Current mirror circuits

A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line

Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

Signal preserve in MRAM during reading

In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.

MRAM cross-point memory with reversed MRAM element vertical orientation

In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The variable resistance circuits are kept at the increased resistance levels during an initial turn-on time period during which a selected memory cell may conducts a current spike. The increased resistance levels of the variable resistance circuit may operate to reduce or limit the width of the current spike. In response to the initial turn-on time period ending, the variable resistance circuits are set back to low resistance levels to facilitate subsequent sense results detection events and program operations.

Resistance and gate control in decoder circuits for read and write optimization

Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Write set operation for memory device with bit line capacitor drive

A bit line read voltage generator may operate in a high drive strength or current mode to drive a selected bit line voltage to a read selected bit line voltage at a high level, and then may switch to operating in a low drive strength or current mode. Doing so may control, such as by limiting, the amount of cell current if the selected memory cell turns on, reducing the likelihood of false writes. Also, a word line read voltage generator may operate in a high drive strength or current mode to ramp up a selected word line voltage level, and then may switch to operating in a low drive strength or current mode to shorten the time for a global selected word line voltage to decrease to below a trip level and/or to control an amount of the cell current when the selected memory cell turns on.

Multiple-mode current sources for sense operations

The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor 'on pitch' which fits between two metal lines traversing the array tile.

Bi-directional RRAM decoder-driver

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vof the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire.

Ovonic threshold switch (OTS) driver/selector uses unselect bias to pre-charge memory chip circuit and reduces unacceptable false selects

The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Growing community of inventors

Nashua, NH, United States of America

Thomas Michael Trent