Imagination Technologies Limited

Thomas Michael Rose

Simon Thomas Nield

Luca O Iuliano

Robert McKemey

Theo Alan Drane

Max Freiburghaus

Robert Mckemey

A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by The hardware logic comprises a plurality of multipliers and adders arranged to implement a m-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Iterative estimation hardware

Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

Sorting memory address requests for parallel memory access using input address match masks

A binary logic circuit for determining y=x mod(2−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.

Performing constant modulo arithmetic

A method of selecting, in hardware logic, an ilargest or a psmallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the riteration, the method comprises: summing an (m−r)bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rbit of the selected number is determined and output and additionally the (m−r−1)bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Selecting an Ilargest or a Psmallest number from a set of n m-bit numbers

A method of selecting, in hardware logic, an ilargest or a psmallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the riteration, the method comprises: summing an (m&#x2212;r)bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rbit of the selected number is determined and output and additionally the (m&#x2212;r&#x2212;1)bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m&#x2212;r)bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Selecting an ith largest or a pth smallest number from a set of n m-bit numbers

A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.

Data selection for a processor pipeline using multiple supply lines

A binary logic circuit for determining y=x mod(2&#x2212;1), where x is an n-bit integer, y is an m-bit integer, and n&#x3e;m, includes reduction logic configured to reduce x to a sum of a first m-bit integer &#x3b2; and a second m-bit integer &#x3b3;; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by &#x3b2;; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by &#x3b3;; and the binary value 1.

Selection of data for processor pipelines using multiple supply lines wherein in one of two modes the same data is supplied to both inputs of a processing element

Sorting memory address requests for parallel memory access

A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2&#xb1;1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2&#xb1;1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.

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Hertfordshire, United Kingdom

Thomas Michael Rose