Nvidia Corporation

Thomas Melvin Ogletree

Christopher James Goodman

Henry Packard Moreton

David Conrad Tannenbaum

Andrew D Bowen

Craig Michael Wittenbrink

Robert W Gimby

Abhijat Ranade

Ziyad Sami Hakura

Vimal S Parikh

Roger L Allen

Dominic Acocella

Alan Menezes

Robert J Hasslen

Timothy J McDonald

Pranav Vaidya

Scott R Whitman

Yogesh Kulkarni

Gregory Paul Smith

Shounak Kamalapurkar

Gongyu Zhou

Jin Ouyang

Various embodiments include a system for generating performance monitoring data in a computing system. The system includes a unit level counter with a set of counters, where each counter increments during each clock cycle in which a corresponding electronic signal is at a first state, such as a high or low logic level state. Periodically, the unit level counter transmits the counter values to a corresponding counter collection unit. The counter collection unit includes a set of counters that aggregates the values of the counters in multiple unit level counters. Based on certain trigger conditions, the counter collection unit transmits records to a reduction channel. The reduction channel includes a set of counters that aggregates the values of the counters in multiple counter collection units. Each virtual machine executing on the system can access a different corresponding reduction channel, providing secure performance metric data for each virtual machine.

Generating power efficient secure multiclient performance monitoring data

A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor can include a state machine. The state machine can be implemented via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes information indicating a state transition condition and output signals. The state transition condition includes a current state and input signals required to meet the condition. The output signals include a next state, one or more counter actions, and one or more triggers. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. The state machine data entries can be written and re-written by a user.

Programmable state machine for a hardware performance monitor

One embodiment of the present invention sets forth a method for analyzing the performance of a graphics processing pipeline. A first workload and a second workload are combined together in a pipeline to generate a combined workload. The first workload is associated with a first instance and the second workload is associated with a second instance. A first and second initial event are generated for the combined workload, indicating that the first and second workloads have begun processing at a first position in the graphics processing pipeline. A first and second final event are generated, indicating that the first and second workloads have finished processing at a second position in the graphics processing pipeline.

Triggering performance event capture via pipelined state bundles

The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Culling before setup in viewport and culling unit

Graphics processing devices and methods are provided for culling small primitives that do not cover any pixels. A boundary (e.g., a diamond) is defined around a pixel center, with pixel coverage being determined for some types of primitives based on whether the boundary is crossed. The boundaries divide the raster into internal regions and external regions. Each region is assigned a unique canonical identifier. Each vertex of a primitive is assigned the canonical identifier corresponding to the region that contains that vertex. The canonical coordinates of the vertices are used to cull primitives that do not satisfy the boundary crossing coverage rules for any pixels.

Diamond culling of small primitives

The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Cull before attribute read

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Lakeway, TX, United States of America

Thomas Melvin Ogletree