Infineon Technologies Ag

Intel Corporation

Apple Inc.

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Intel IP Corporation

Thomas Mayer

Christian Wicpalek

Peter Preyler

Stefan Tertinek

Linus Maurer

Thomas Bauernfeind

Zdravko Boos

Volker Neubauer

Jongmin Park

Burkhard Neurauter

Andreas Roithmeier

Karim M Megawer

Christian Drewes

Bernd-Ulrich Klepser

Christian Mayer

Nick Shute

Ram S Kanumalli

Tobias Buckel

Tindaro Pittorino

Giuseppe Patane

Markus Scholz

Yangjian Chen

Stephan Henzler

Werner Schelmbauer

Thorsten Tracht

Victor Da Fonte Dias

Andreas Mayer

Jan M Zaleski

Günter Märzinger

Rainer Dirk Kreienkamp

Jens Kissing

Thomas Gustedt

Hans Geltinger

Christoph Preissl

Benjamin Lindner

Juergen Koechl

Christoph S Preissel

An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

Electronic devices having wireless transceivers with reference clock selection

To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

Systems and methods for PLL duty cycle calibration

This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

Systems and methods for PLL gain calibration

This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector

A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.

Receiver with tunable receiving chain

An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Apparatus and method for generating an oscillation signal, mobile communication systems and mobile device

Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

Dithering for spur reduction in local oscillator generation

In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.

Polar modulation systems and methods

An apparatus and a method for synchronizing a Digital Frequency Shift (DFS) for a signal to be transmitted over a wireless channel are disclosed. For example, the method, by a synchronizer, transmits a DFS trigger to a Digital Front End (DFE) processor and a Local Oscillator (LO) trigger to an LO in a synchronous manner, the method, by the DFE processor, applies a DFS on received data in response to receiving the DFS trigger, the method, by the LO, applies a complementary shift on a carrier signal in response to receiving the LO trigger, the method, by the upconverter, digital-to-analog converts and radio frequency modulates the digital frequency-shifted received data and the complementary-shifted carrier signal. In another example, the method, by the synchronizer, transmits a phase error to a phase error corrector that performs a phase error correction.

Synchronizing a digital frequency shift

Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator () configured to output provide a clock signal having a predefined average clock rate, a reference signal generator () configured to provide a reference signal, and a clock divider () configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal

A digitally controlled oscillator (DCO) circuit is disclosed. The DCO circuit comprises a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword. In some embodiments, the tuning circuit comprises an integer tuning circuit configured to process the integer tuning codeword and a fractional tuning circuit configured to process the fractional tuning codeword, in order to implement the input tuning codeword. In some embodiments, the integer tuning codeword comprises an integer tuning range associated therewith and the fractional tuning codeword comprises a fractional tuning range associated therewith. In some embodiments, the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.

Redundant DCO tuning with overlapping fractional regions

A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

System and a method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop

One embodiment covers an apparatus for generating a transmission signal. The apparatus may include a signal generator that generates a first signal with a first frequency spectrum comprising a carrier frequency; a power control unit that provides a power information signal which represents a signal level of the transmission signal residing at the carrier frequency; a first signal shaper for noise-shaping the first signal based on the power information signal to form a second signal which has a noise component in at least one frequency range remote from the carrier frequency, the noise component of the second signal being from one or more signal components associated with the carrier frequency; and a signal output that provides the second signal in the form of a transmission signal.

Generation of a transmission signal

This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

Digital-to-time converter spur reduction

Growing community of inventors

Linz, Austria

Thomas Mayer