Texas Instruments Corporation

Thomas Matthew LaBella

Michael G Amaro

Saurav Bandyopadhyay

Robert Allan Neidorff

Jeffrey Anthony Morroni

Michael Thomas DiRenzo

Huy Le Nhat Nguyen

Methods and apparatus to provide an adaptive gate driver for switching devices are disclosed. An example apparatus includes an electrical switch to drive an electrical system; a condition characterizer to select a drive strength based on a first system parameter corresponding to the electrical system, the first system parameter including at least one of an input voltage corresponding to the electrical switch, an output current corresponding to the electrical switch, or a process variation of the electrical switch; and a driver to generate an output having a current corresponding to the selected drive strength.

Methods and apparatus to provide an adaptive gate driver for switching devices

A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.

Switch-mode power supply with load current based throttling

Timing circuitry causes: a first closed signal on a first switch control output before a signal on a second switch control output changes from a second closed signal to a first open signal; the first switch control output to provide a second open signal after a first selected time after the second switch control output changes from the second closed signal to the first open signal; and a third switch control output to provide a third closed signal a second selected time after the first switch control output changes from the first closed signal to a third open signal. A beginning of the first closed signal to a beginning of the first open signal is based on a later of: a current through a switch connected to the second switch control output exceeding a threshold current; and a clocked time after the beginning of the first closed signal.

Methods and apparatus for adaptive timing for zero voltage transition power converters

A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.

Adaptive synchronous rectification in a voltage converter

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.

Load release detection circuit

Described examples include a method of controlling a power converter including executing a plurality of cycles. Each cycle includes turning on a first switch during a first period, the first switch coupled between a power supply and an output inductance; turning on a second switch during a second period, the second switch coupled between an output inductance and ground; turning on a third switch at a first time during the second period, the third switch coupled between the power supply and an auxiliary inductance; and turning on a fourth switch on at a third time after the second time, the fourth switch coupled the auxiliary inductance and ground. The second period ends at a third time period after the first time based on a later of an overlap time and a current through a switch connected to the second switch current handling terminal exceeding a threshold current.

An example apparatus includes a first switch having a control terminal, coupled to a voltage source and coupled to a switch node; a second switch having a control terminal, coupled to the switch node and to a voltage reference; a first inductor coupled to the switch node and to a load; a third switch having a control terminal, coupled to the voltage source and to an auxiliary node; a fourth switch having a control terminal, coupled to the auxiliary node and to the voltage reference; a second inductor coupled to the switch node and the auxiliary node; a fifth switch having a control terminal, coupled to the switch node and to the auxiliary node; and timing circuitry configured to output signals to the control terminals of the first switch, the second switch, the third switch, the fourth switch and the fifth switch to supply current to the load.

In a method arrangement, providing a zero voltage transition circuit including an input node, an output node, a switch node, an output inductor coupling the switch node and output node, an output capacitor coupling the output node and ground, a first switch coupling the input node and switch node, a second switch coupling switch node and ground, a first auxiliary switch coupling the input node to an auxiliary node, a second auxiliary switch coupling the auxiliary node to ground, and an auxiliary inductor coupling the auxiliary node to the switch node; closing the first auxiliary switch to couple the input to the auxiliary node; subsequently, when a current is below a cutoff threshold, opening the second switch; after a first delay period, opening the first auxiliary switch and closing the second auxiliary switch; and after a second delay period, closing the first switch. Apparatus and additional method arrangements are disclosed.

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Dallas, TX, United States of America

Thomas Matthew LaBella