Hewlett-packard Company

Agilent Technologies, Inc.

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Thomas M Walley

Charles E Moore

Brian James Misek

Mark Alan Anderson

Larry S Metz

Michael John Brosnan

Travis N Blalock

Rajeev Badyal

Richard A Baumgartner

Robert M Thelen

Ran-Fun Chiu

Sui-hing Leung

Li Ching Tsai

Jeffery M Davis

Jacob Lee Bell

Michael Farmer

Richard A Baugh

Allen C Norskog

Robert A Zimmer

James S Ignowski

Kenneth R Stafford

William L Pherigo, Jr

A circuit for skewing differential signals includes a coarse adjustment stage configured to receive a differential input signal having a true component and a complement component, the coarse adjustment stage configured to impart a first controllable delay to at least one of the true component and the complement component of the differential signal, and a fine adjustment stage configured to impart a second controllable delay to at least one of the true component and the complement component of the differential signal, the second controllable delay having a resolution different than a resolution of the first controllable delay, the first controllable delay and the second controllable delay providing a timing skew between the true component and the complement component of the differential signal.

System and method for pre-skewing timing of differential signals

A method and system of imaging an object. First, movement information of the object is determined by using a navigation sensor array and a navigation engine. Based on the movement information, an imaging sensor strobe signal is selectively asserted to control an imaging sensor array. In response to an asserted imaging sensor strobe signal, the imaging sensor array captures sub-images of the object. The imaging sensor array has a plurality of pixels for imaging a portion of the object at one time. The plurality of sub-images are captured successively by the imaging sensor array as the object moves with respect to the imaging sensor array. Then, a composite image of the object is generated based on the captured sub-images.

Fingerprint imager

An apparatus for controlling the position of a screen pointer for an electronic device having a display screen includes a light source for illuminating an imaging surface, thereby generating reflected images. The apparatus includes a single chip for receiving the reflected images, generating digital representations of the reflected images, and generating a first set of movement data based on the digital representations of the reflected images. The first set of movement data is indicative of relative motion between the chip and the imaging surface. The single chip includes a serial interface for outputting motion data in a serial format based on the movement data.

One chip USB optical mouse sensor solution

An apparatus for sensing three-dimensional relative movement includes a movable motion sensor including a first and a second two-dimensional array of photo detectors. At least one lens directs far-field images onto the first and the second arrays of photo detectors. The sensor is configured to generate digital representations of the far-field images and to generate three-dimensional relative movement data based on the digital representations of the far-field images. The movement data is indicative of motion of the sensor in three dimensions.

Apparatus and method for three-dimensional relative movement sensing

A time delay system and method utilize an accurate clock signal with a known frequency to calibrate an inaccurate clock signal that will be used to generate a desired time delay. In the case that the frequency of the inaccurate clock signal is lower than the frequency of the accurate clock signal, the number of cycles of the accurate clock signal that occur during a predetermined portion of the inaccurate clock signal is used to calibrate the inaccurate clock signal. Alternately, if the frequency of the inaccurate clock signal is higher than the frequency of the accurate clock signal, the number of cycles of the inaccurate clock signal that occur during a predetermined portion of the accurate clock signal is used in the calibration. The calibrated inaccurate clock signal is then utilized to generate an accurate time delay.

Accurate time delay system and method utilizing an inaccurate oscillator

Disclosed is a system and method for generating a data sequence from a two frequency coherent phase signal. The system comprises an integrated magnetic read channel that includes a magnetic reader circuit configured to generate an analog two frequency coherent phase (F2F) signal from a magnetic strip, the analog F2F signal having a number of alternating positive and negative peaks having a respective positive and negative transitions therebetween. The output of the magnetic reader circuit is applied to an analog-to-digital converter configured to convert the analog F2F signal into a digital F2F signal. Thereafter, the digital F2F signal is applied to a peak detector configured to identify the alternating negative and positive peaks. The magnetic read channel also includes a transition calculator configured to determine a transition time between each of the consecutively positioned alternating positive and negative peaks, and a frequency locked loop configured to determine a transition type for each of the transition times. Finally, the output of the frequency locked loop is applied to a data separator configured to determine a data value from the transition types.

Digital magnetic read channel and method

An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Analog implementation of a partial response maximum likelihood (PRML)

A fully-integrated CMOS peak detector stores the peak amplitude of an input signal using an on-chip storage capacitor. The fully-integrated CMOS peak detector includes a delay buffer, a transfer gate and a comparator. A discharge controller is used to step-down the peak amplitude stored on the on-chip storage capacitor some predetermined amount. The discharge controller includes a switched capacitor circuit which is placed in series with the storage capacitor such that the two capacitors act as a capacitive voltage divider to produce a predictable fraction of the acquired peak amplitude. Multiple peaks can be determined and/or stored by using multiple fully-integrated CMOS peak detectors in conjunction with a single comparator. A multiplexer is used in this configuration to control the multiple peak detectors.

CMOS peak amplitude detector

Growing community of inventors

Loveland, CO, United States of America

Thomas M Walley