Micron Technology Incorporated

Thomas M Trent

Ward D Parkinson

Wen-Foo Chern

Kevin G Duesman

Gary M Johnson

Tyler A Lowrey

Leland R Nevill

Stanley N Protigal

Zhitong Chen

Ward M Parkinson

James E O'Toole

Web-Foo Chern

An extensive network of N-channel transistor formed capacitor, with one node tie directly to V power bus and the other node directly V power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Chip decoupling capacitor

A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.

Integrated circuit module having on-chip surge capacitors

An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-chip capacitors of the memory devices in parallel, sufficient capacitance is provided to stabilize current to all of the memory devices.

Memory module having on-chip surge capacitors

An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.

Depletion mode chip decoupling capacitor

A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

Pull up circuit for digit lines in a semiconductor memory

A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

Pull up circuit for sense lines in a semiconductor memory

A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.

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Boise, ID, United States of America

Thomas M Trent