International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Thomas M Shaw

Vincent James McGahay

Michael Wayne Lane

Xiao Hu Liu

Deborah A Neumayer

Robert B Laibowitz

Chih-Chao Yang

Alfred Grill

Conal Eugene Murray

Katherine Lynn Saenger

Anthony K Stamper

Daniel C Edelstein

Timothy Joseph Dalton

Wilbur David Pricer

Charles Thomas Black

Son Van Nguyen

Ping-Chuan Wang

Matthew Earl Colburn

Edward Crandal Cooney, Iii

Hazara Singh Rathore

James William Adkisson

Stephen McConnell Gates

Elbert Emin Huang

Andrew Herbert Simon

John Anthony Fitzsimmons

Satyanarayana Venkata Nitta

Randy William Mann

Jeffrey P Gambino

Haining S Yang

Keith Kwong Hon Wong

Sampath Purushothaman

Cyril Cabral, Jr

Griselda Bonilla

Peilin Song

Franco Stellari

Eric Gerhard Liniger

Mukta G Farooq

Dirk Pfeiffer

Ronald G Filippi

David Arlen Elko

Thomas Anthony Wassick

Chao-Kun Hu

Mark C H Lamorey

Darryl D Restaino

William Francis Landers

Robert Rosenberg

Lawrence Alfred Clevenger

Christian Lavoie

Paul Michael Solomon

Stephen Mark Rossnagel

Yun-Yu Wang

Dennis Merton Newns

David Brian Stone

Matthew Warren Copel

Howard Smith Landis

James J Demarest

Glenn John Martyna

Bruce Gordon Elmegreen

Huilong Zhu

Tak H Ning

Michael S Gordon

Timothy Harrison Daubenspeck

Kirk David Peterson

Christopher David Muzzy

Kenneth Parker Rodbell

Chandrasekharan Kothandaraman

Bucknell Chapman Webb

Sanjay C Mehta

Young-Ho Kim

Anthony J Annunziata

Fuad Elias Doany

Christos Dimitrios Dimitrakopoulos

George Frederick Walker

Emanuel Israel Cooper

David L Questad

Robert Hannon

Qiang Huang

Shaji Farooq

Sarah Huffsmith Knickerbocker

James Patrick Doyle

Ian D Melville

Gregory M Fritz

Eric Peter Lewandowski

Robert Anthony Rita

Lynne Marie Gignac

Dureseti Chidambarrao

Takeshi Nogami

Michael A Gaynes

Timothy Dooling Sullivan

Sandra Guy Malhotra

Roy Rongqing Yu

Jae Hun Kim

Kim Yang Lee

Hosadurga K Shobha

Erdem Kaltalioglu

John David Baniecki

Shidong Li

Hormazdyar M Dalal

Roy Arthur Carruthers

Christopher Carr Parks

Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Techniques to improve reliability in Cu interconnects using Cu intermetallics

A semiconductor device that includes a substrate having integrated circuits; a plurality of metallization layers on the substrate, the plurality of metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure extending through the plurality of metallization layers; a trench extending through the plurality of metallization layers and adjacent to the crack stop structure, the trench filled with a material that creates compressive stresses between the filled trench and the adjacent metallization layers to form a compressive zone adjacent to the crack stop structure. Also disclosed is a method for forming the semiconductor device.

Compressive zone to reduce dicing defects

Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.

Integrated circuit defect detection using pattern images

A semiconductor device which includes a substrate having integrated circuits; and metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure. The crack stop structure includes a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; and a top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion.

Step pyramid shaped structure to reduce dicing defects

A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

Piezoelectronic switch device for RF applications

A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.

Strain monitoring of MRAM arrays

Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Integrated time dependent dielectric breakdown reliability testing

Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.

Controlling fragmentation of chemically strengthened glass

A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface.

Volumetric integrated circuit and volumetric integrated circuit manufacturing method

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Peekskill, NY, United States of America

Thomas M Shaw