Compaq Computer Corporation, Inc.

Cirrus Logic Inc.

Thomas M Ogletree

Michael J Dougherty

Ralph K Williamson

Mark Alan Einkauf

Stephen M Zaudtke

Rodney J Pesavento

A method and apparatus for processing a plurality of bits stored in a memory, where the plurality of bits represent a cumulative pattern to be printed by reproducing the stored bits in a fast scan direction. Each bit stored in memory has a state (e.g., binary 0 or 1). As an example, the method selects a first subset of the plurality of bits, wherein the first subset forms a first pattern and has a center bit. Further, the method selects a second subset of the plurality of bits, wherein the second subset forms a second pattern and has a center bit coextensive with the center bit of the first subset. Next, the method determines, based on the states of the bits of the first pattern, whether the state of the center bit should be printed in the same state as it is stored in the memory. In addition, the method determines, based on the states of the bits of the second pattern, whether the state of the center bit should be printed in the same state as it is stored in the memory.

Anti-aliasing apparatus and method using pixel subset analysis and

Method and apparatus are disclosed for increasing the speed of mathematical operations in a processor core. The invention increases the speed of mathematical operations by delivering a first instruction indicating the total number of clock cycles a sequence of operations will occupy. On a first subsequent cycle, a different instruction is provided including operand addresses. Other instructions containing operand addresses may be provided on subsequent cycles. Alternatively, an internal pointer may be dynamically changed each cycle to provide new operand addresses. The operands are then retrieved and operated on while other operands are generated.

Method for speeding mathematical operations in a processor core

A polygon vertex sorting circuit for a three dimensional graphics computer system. The system of the present invention includes a swap configuration circuit coupled to receive a plurality of vertex address corresponding to a plurality of vertices of a polygon. The swap configuration circuit is coupled to an address input bus to receive the plurality of vertex addresses. An address output interface circuit is coupled to the swap configuration circuit. The address output interface circuit interfaces the output of the swap configuration circuit with an address output bus. A control circuit is coupled to the swap configuration circuit and the output interface circuit. The control circuit sorts the plurality of vertices by configuring the swap configuration circuit and the address output interface circuit to output a swapped vertex address via the address output bus in response to receiving one of the plurality of vertex addresses via the address input bus.

Method and system for efficient register sorting for three dimensional

A circuit performs controlled multiplication, shifting, and accumulation operations. A sequence of pairs of input operand signals and corresponding arithmetic control signals are synchronously supplied to the circuit by an external controller. Arithmetic control values include a downshift value (DV) for controlling shifting operations and an accumulate number (AN) for controlling accumulation operations. The circuit includes n booth multipliers (BMs) for receiving the sequenced information and a first multiplexer having n inputs each coupled to a BM output. Each BM has a BM memory control unit. For rounding purposes during downshifting, each P register of each BM is primed before each multiply operation. An internal control circuit monitors the status of each BM. If all of the BMs are 'busy' and another multiply request arrives, then a stall signal is sent to the external controller. When the status of BM.sub.i is 'finished,' the internal control circuit selects the output of BM.sub.i to output through the first MUX. A downshift circuit is controlled to shift the output of the first MUX according to the corresponding DV. A plurality of m accumulators each have an input coupled to receive a downshift circuit output. The AN signal is used to select which of the plurality of m accumulators to enable via an accumulate select bus. Each of the m accumulators may be implemented with an adder and a register. The external controller can select one of the m accumulators to receive the final product value.

Parallel multiply accumulate array circuit

A method and apparatus for conserving a substance dispensed by a printer engine for forming print on a media. As an example, the method stores a plurality of bits in a memory, the plurality of bits representing a cumulative pattern to be printed by reproducing the bits on the media. Each bit is either in a first memory state or a second memory state. The method further selects a subset of the plurality of bits, wherein the subset forms a first pattern and has a center bit. If each of the plurality of bits of the subset is in the first memory state, the method outputs to the printer engine a print bit corresponding to the center bit and in a print state which is opposite the memory state of the center bit. If, however, at least one of the plurality of bits of the subset is in the second memory state, the method outputs to the printer engine a print bit corresponding to the center bit and in a print state the same as the memory state of the center bit.

Toner saver using anti-aliasing apparatus and methodology

A method processes a plurality of bits stored in a first memory and representing an image to be printed by reproducing the bits in a fast scan direction. The method includes the step of reading a plurality of groups from the first memory into a second memory, wherein each of the groups comprises a number of bits greater than one bit and is stored in the second memory in the fast scan direction, and wherein each group is read one group at a time. Further, the method includes copying a predetermined number of bits from each of the plurality of groups to a sample storage area. After the copying step, the method samples the bits of the copied groups wherein the sampled bits form a pattern having a center bit having a binary state. Finally, after the sampling step, the method outputs a print signal representative of the binary state if the pattern does not match a predetermined pattern, or outputs a print signal different than the binary state if the pattern matches a predetermined pattern.

Anti-aliasing apparatus and method using fast scan-line memory mapping

A printer has test circuitry external to its processor to test memories used inside the printer. The test is initiated by the processor by signalling the test circuitry. The test circuitry stores a first sequence in each memory then reads the sequence from the memory and compares the memory's data to the original sequence. The test is repeated with a second sequence which is the logical inverse of the first sequence. If an error occurs, a flag is set. When the test is complete, the processor is notified. The processor can check the error flag to determine whether the test was successful.

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Austin, TX, United States of America

Thomas M Ogletree