National Semiconductor Corporation

Glacier Microelectronics

Other

Fairchild Camera and Instrument Corp.

Jet City Electronics, Inc.

Thomas M Luich

Scott K Pickett

Arthur L Swift, Iv

David A Byrd

William K Waller

Jay R Chapin

Michael S Millhollan

Huard, Jeffry M

This disclosure relates to a programmable wideband, LC Tuned, Voltage Controlled Oscillator with continuous center frequency select, and independent configuration of amplitude and tuning gain. The programmability can be via on chip non-volatile memory, or through data shifted into the part and stored via a data bus.

VCO with independently controllable parameters

An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, circuitry for producing an oscillatory output signal having a peak voltage of V volts uses MOS transistor circuitry transistors of which are designed for a maximum port-to-port voltage of substantially less than V volts. A first inverter chain is coupled to an input signal to produce a predriver output signal. A second inverter chain of multiple of inverters including a first inverter produces a driver output signal. Circuitry is provided for AC-coupling the predriver output signal to the second inverter chain, it being configured to translate the predriver output signal to a higher voltage range to produce a translated predriver output signal. A driver transistor is controlled using the driver output signal to produce the oscillatory output signal, and circuitry coupled to the driver output transistor ensures that no port-to-port voltage of the driver output transistor exceeds the maximum port-to-port voltage.

Low-noise PECL output driver

An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, the integrated circuit output driver is fabricated in a process having thin-gate MOS transistors and thick-gate MOS transistors and includes a predriver circuit, a level shifter circuit, and a driver circuit. The predriver circuit is formed predominantly of thin-gate transistors, and the driver circuit is formed predominantly of thick-gate transistors. In other embodiments, a low-pass power supply filter is provided. In still other embodiments, a voltage regulator circuit is provided, wherein an operating potential of at least one of the predriver circuit and the level shifter circuit is less than the specified supply voltage. In one embodiment, the voltage regulator circuit produces: i) a reduced internal supply voltage that is applied to the predriver circuit; and ii) an elevated ground voltage that is applied to the level shifter circuit.

The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations.

High yielding, voltage, temperature, and process insensitive lateral poly fuse memory

An Electrically Erasable Programmable Read Only Memory (EEPROM) cell uses a single standard NMOS (or PMOS) transistor with its gate connected to a Metal-Insulator-Metal, or Poly-Insulator-Poly capacitor such that a floating gate is formed. The floating gate is programmed and erased via Fowler-Nordheim tunneling.

Electronically erasable memory cell using CMOS technology

A metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current includes drain and source regions separated by a channel, a drain terminal over a portion of the drain region, a source terminal over a portion of the source region and a gate terminal opposite the channel. An oxide layer is deposited over the remaining portions of the drain and source regions, as well as on the adjacent vertical sides and top edges of the drain, source and gate terminals. A silicide layer is deposited over the gate terminal between the oxide-covered top edges thereof and over the drain and source terminal up to the oxide-covered top edges thereof. With oxide over the drain source regions instead of silicide, parasitic Schottky diodes are avoided, thereby eliminating leakage current due to such parasitic elements. Additionally, the oxide layer over the drain and source regions blocks pldd and nldd diffusions, thereby preventing impingement of the drain and source regions under the gate and adjacent oxide spacers and thereby significantly reducing leakage current due to band-to-band tunneling.

MOSFET with reduced leakage current

A low leakage, metal oxide semiconductor field effect transistor (MOSFET) charge pump circuit includes P- and N-MOSFET current mirrors, P- and N-MOSFET current switches and an output node. The P-MOSFET current mirror sources an output current which is switched by the P-MOSFET current switch in accordance with a pump-up control signal to provide a pump-up current. The width of the channel of the P-MOSFET current switch is substantially less than the sum of the widths of the channels of the P-MOSFETs of the P-MOSFET current mirror. The N-MOSFET current switch, in accordance with a pump-down control signal, switches a pump-down current which is sunk by the N-MOSFET current mirror. The width of the channel of the N-MOSFET current switch is substantially less than the sum of the widths of the channels of the N-MOSFETs of the N-MOSFET current mirror. The output node couples the P- and N-MOSFET current switches and receives the pump-up current and provides the pump-down current to provide a net charge pump signal suitable for use by a voltage controlled oscillator within a phase lock loop.

Cascode switched charge pump circuit

An output buffer circuit advantageously uses a simple integrated circuit package including two separate ground leads for connection to an externally supplied ground voltage. The relatively large pull down current which passes through the pull down transistor of one or more output buffers are fed through a first ground lead of the lead frame to the external ground and the remaining circuitry is connected to the external ground through the second ground lead of the lead frame. The transients in the pull down current will cause ground bounce which affects the pull down transistor only, and not the remaining components of the output buffer. In this manner, base drive to the output pull down transistor is not decreased due to ground bounce, and the high to low transition of the output voltage is not degraded by the presence of ground bounce. In an alternative embodiment, the amount of ground bounce is controlled to provide a desired characteristic of the output transition.

Ground bounce isolation and high speed output circuit

A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Method for operating a multiple page programmable logic device

In accordance with teachings of this invention a novel sense amplifier is provided. The sense amplifier includes an enable circuit which receives an enable input signal. This enable circuit includes a constant current source which consumes a small amount of power. The enable circuit provides an output signal which serves to disable the output pull up and pull down transistors of the sense amplifier, thereby providing a high impedance output signal. At the same time, the disabling output signal from the enable circuitry powders down the read circuitry, thereby minimizing power consumption.

High speed data/tri-state sense circuit

Multiple page programmable logic architecture

An ECL input buffer is particularly well-suited for use with logic arrays where a large amount of current must be sunk by the row line, for example, when vertical fuse devices are used in an AND array. The input buffer provides means for pulling down the row line such that the entire amount of current sunk by the input buffer from the row line need not pass through a current source, thereby minimizing current consumption of the input buffer. A pull down current source is used which causes a pull down transistor to turn on, thereby pulling down the row line while requiring only the base current of the pull down transistor to be consumed by the current source. A pull up device is utilized and means are included for insuring that the pull up and pull down devices are not both turned on simultaneously, thereby preventing a current spike through the pull up and pull down means.

High speed ECL input buffer for vertical fuse arrays

A novel sense amplifier is taught which minimizes power consumption by causing selected current sources to conduct current only when an input signal of a selected state is present. The speed of the circuit is fast because capacitance on the critical nodes is minimized by connection of fewer transistors to the critical nodes, as compared with the prior art.

Growing community of inventors

Campbell, CA, United States of America

Thomas M Luich