International Business Machines Corporation

Thomas M Lepsic

Sebastian Theodore Ventrone

David James Hathaway

John Maxwell Cohn

Alvar Antonio Dean

Scott Alan Tetreault

Amir H Farrahi

Jagannathan Narasimhan

David E Lackey

Susan K Lichtensteiger

Patrick Edward Perry

W Riyon Harding

An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum same-direction switching probability &#x3c6;or has an opposite-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability &#x3c6;. The first wire and the second wire satisfies at least one mathematical relationship involving Land Wwhere Wis defined as a spacing between the first wire and the second wire, and Lis defined as a common run length of the first wire and the second wire.

Wiring optimizations for power

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.

Method and apparatus for providing bus arbitrations in a data processing system

Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into &ldquo;bins&rdquo;, which are areas of the design. In this way, a semiconductor chip design may be &ldquo;sliced&rdquo; into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

In integrated circuit (IC) designs, a component of power consumed may be represented as Power&equals;&frac12; FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

Growing community of inventors

Jeffersonville, VT, United States of America

Thomas M Lepsic