Data General Corporation

Other

Convex Computer Corporation

Intuit, Inc.

Thomas M Jones

Brett L Bachman

Richard G Bratt

John F Pilat

Craig J Mundie

David H Bernstein

Steven J Wallach

Stephen I Schleimer

Gerald F Clancy

Richard A Belgard

Edward S Gavrin

Ronald H Gruner

Michael S Richmond

Walter A Wallach, Jr

Lawrence H Katz

John K Ahlstrom

Douglas M Wells

James T Nealon

David L Houseman

Steven Jeffrey Wallach

David A Farber

David M Chastain

Harold Wallace Dozier

Arthur T Kimmel

Gary Davidian

Ward Baxter, Ii

Alan D Gant

E Wayne Lytle

Stephen R Redfield

Jeffrey H Gruger

David A Nobles

Gary Belgrave Gostin

Jame Yao

Ian J Fettes

Michael B Druke

Weldon L Ransbarger

James R Weatherford

John W Clark

Paul Bowden

Jonathan Michael Talan

Charles J Young

Shawn S Huang

James E Mankovich

Mark A Johnson

Steven B Sather

Steven M Haeffele

William N Coder

Michael C Harris

Frederick M Mozer

Michael E Sydow

Larry W Spry

Douglas M Well

Louis E Drew

Harry J Crofton

Harold D Shelton

Philip C Goundry

Robert B Kolstad

William H Wallace

Steven M Rowan

Kent A Fuka

Frank J Marshall

Gilbert J Hansen

John M Golenbieski

Jeffrey O Pfeiffer

Gaynel J Lockhart

Gerald Matulka

A method for managing trust level in a community comprises selecting a data provider and a data entry entity from the community, wherein the community comprises data providers providing provided data, data entry entity providers providing data entry entities, and reviewers, obtaining provided data and a trust level of the provided data from the data provider, retrieving a data entry quality level of the selected data entry entity from a community system, wherein the community system comprises data entry quality levels corresponding to the data entry entities, and determining a data source trust level based on the trust level of the provided data and the data entry quality level of the selected data entry entity, wherein the data source trust level indicates validity of data produced by the selected data entry entity.

Community to support the definition and sharing of source trust level configurations

Exemplary embodiments of sink support systems. An exemplary embodiment includes a cross-member having respective first and second cross-member attachment structures attached at respective ends. First and second mount brackets are configured for attachment to a vertical surface of the support structure. Each of the cross-member attachment structures is configured to engage a corresponding mount bracket to vertically support the cross-member. The cross-member has a plurality of leveling devices to support the sink.

Sink support systems

A sink setting cross-member supports a non-linear sink support surface relative to a support structure. In an exemplary embodiment, the cross-member includes a first bracket portion at a first bracket end, and a second bracket portion at a second bracket end. A support portion is disposed between the first bracket portion and the second bracket portion.

Sink setting systems for offset and other sinks

An exemplary embodiment of a bracket system for supporting a shelf or countertop includes first and second separate elongated bracket members, each having a connection end and a distal end. The connection end of the first bracket member is adapted for removable attachment to the connection end of the second bracket member. Each of the first and second elongated bracket members includes fastener members for fixing the first and second bracket members together at the connection ends.

Bracket system

An exemplary embodiment of a system for mounting a sink to a support structure includes first and second support members. The first and second support members are adapted for fitting together along a range of positions to provide a variable length sink support system. Leveling devices are adapted for engagement with the support member and for contacting sink surfaces.

Sink support system

A single LNG facility, and operating method therefor, capable of efficiently producing LNG products that meet the varying specifications of different LNG markets.

LNG facility providing enhanced liquid recovery and product flexibility

A residue collector is adapted for coupling to a prep-board. The collection perimeter encompasses a reservoir and has support members for laterally and perpendicularly supporting the prep-board. The support members are inboard of the collection perimeter.

Preparation surface with residue receptacle

A suction-eliminated waste receptacle for releasing air trapped between the liner member and the container. The suction-eliminated waste receptacle includes a container having a bottom wall and an open top; and also includes a flexible liner member being removably disposed in the container; and further includes a tubular conduit member being disposed in the container between side and bottom walls of the container and the flexible liner member for allowing air to enter between the side and bottom walls of the container and the flexible liner member.

Suction-eliminated waste receptacle

A data processing system which includes a memory and a processor comprising at least two execution units. The system further includes a microcode control unit for storing sequences of microinstructions and an execution microinstruction stack containing at least one stack frame containing the machine state of a first execution unit when the execution of a microinstruction has been interrupted. A memory microinstruction stack is provided to store a plurality of stack frames, stack frames being transferrable between the execution microinstruction stack and the memory microinstructiion stack. The microcode control unit contains sequences of monitor microinstructions and has associated with it a minotor microinstruction stack for storing the machine state of the first execution unit when the execution of a monitor microinstruction has been interrupted. A second execution unit for executing primarily arithmetic microinstructions includes an execution storage unit containing the current machine state of the second execution unit and an arithmetic stack which stores the machine state of the second execution unit when it has executed a previous arithmetic microinstruction. The memory includes a memory arithmetic stack containing further arithmetic stack frames, stack frames being transferrable between the execution storage unit and the memory arithmetic stack. Further an instruction stack is provided for storing the machine state in the processor when execution of a macroinstruction has been interrupted.

Data processing system having unique microinstruction control and stack

A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus ( 16) can interrupt any of the other units. The interrupt process comprises sending an interrupt vector through interrupt lines (66). At the receiving unit the interrupt is identified and the appropriate function carried out. The combination of the communication bus and the interrupt bus (16) comprises an input/output bus for the computer system (10) to provide a high data bandwidth together with flexible operation.

Input/output bus for system which generates a new header parcel when an

An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80). The operand processing unit (10) provides concurrent processing of operands to enhance processing speed. The operands and resultants are handled in a manner such that there is a uniform and sequential flow of operands from a source, such as main memory, and a uniform and sequential delivery of resultants to a destination, such as a memory or input/output device.

Concurrent processing of data operands

A diagnostic circuit is used to test the operation of a complex digital system by transferring operands to and from a plurality of registers (12, 14, 16). In a typical application the registers (12, 14, 16) in operation utilize parallel data transfers. For diagnostic purposes the registers (12, 14, 16) are connected serially and, in response to selected shift commands, data can be shifted either right or left through the registers (12, 14, 16). First and second buses (18, 20) provide serial, bidirectional paths for data transfer between the group of registers (12, 14, 16) and a service processing unit (26). In response to commands generated by the service processing unit (26) the registers (12, 14, 16) can be loaded right or left and read right or left. Whenever data is being read from the registers (12, 14, 16) the output data is recirculated back into the registers such that a complete cycle results in the original state being restored in the registers (12, 14, 16).

Diagnostic circuit

Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Encachement apparatus using two caches each responsive to a key for

A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may determine the location and the format for the data (e.g., an operand) represented by the name.

Digital data processing system having a uniquely organized memory system

A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.

Computer system

Growing community of inventors

Chapel Hill, NC, United States of America

Thomas M Jones