Samsung Electronics Co., Ltd.

Thomas M Henige

Eran Pisek

Shadi Abu-Surra

Zhouyue Pi

Rakesh Taori

Yan E Wang

Gary Xu

Jasmin Oz

Bei Yin

Thirumalarao Voonna

Mehrzad Malmirchegini

Shadi Abu-surra

Methods and apparatuses for coding a codeword. An apparatus for decoding the codeword includes a memory configured to receive the codeword encoded based on a low-density parity check (LDPC) code H-matrix and a two-step lifting matrix and processing circuitry configured to decode the received codeword. An apparatus for encoding the codeword includes memory configured to store information bits to be encoded into the codeword and processing circuitry configured to encode the codeword based on based on a LDPC code H-matrix and a two-step lifting matrix. A code length of the LDPC code H-matrix lifted by the two-step lifting matrix is an integer multiple of 672 bits. The LDPC code block H-matrix may be an IEEE 802.11ad standard LDPC coding matrix. The two-step lifting matrix can be one of a plurality of two-step lifting matrices to generate a family of LDPC codes.

Channel coding framework for 802.11AY and larger block-length LDPC codes for 11AY with 2-step lifting matrices and in-place property

An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.

Apparatus and method for decoding LDPC codes in a communications system

A receiver in a communication system is provided that includes a synchronization module and a channel estimator. The synchronization module is configured to identify an end of a cyclic prefix (CP) in a received signal using slope detection by monitoring a detection metric threshold in the received signal. The channel estimator is configured to estimate a complex noise variance using guard band subcarriers.

High-throughput beamforming MIMO receiver for millimeter wave communication and method

A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.

Freezing-based LDPC decoder and method

A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many code blocks as stages. A controller passes the code blocks between the processing stages at the proper time and in the proper sequence. The controller passes the code blocks through the series of stages in a time-division multiplexed fashion.

System and method for multi-stage time-division multiplexed LDPC decoder

A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a '&#x2212;1', selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.

LDPC code family for millimeter-wave band communications in a wireless network

A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.

Method and system for testing a software-defined radio device

A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2(mod n), 2(mod n) and (22)(mod n), where i=0 to M&#x2212;2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yof the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.

Method and apparatus for efficient modulo multiplication

A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process.

Contention-free parallel processing multimode LDPC decoder

A software-defined radio (SDR) system that operates under a plurality of wireless communication standards. The SDR system comprises a reconfigurable maximum aposteriori probability (MAP) decoder capable of being configured under software control to decode a received data block according to a select wireless communication standard and a reconfigurable interleaver associated with the reconfigurable MAP decoder. The reconfigurable interleaver comprises a reconfigurable interleaver core circuitry capable of being configured under software control to operate according to the selected wireless communication standard and a unified interleaver interface for coupling a defined set of control and bus signals from the reconfigurable MAP decoder to the reconfigurable interleaver core circuitry.

Interleaver interface for a software-defined radio system

An almost regular permutation (ARP) interleaver and method generate interleaved indices in a sequential fashion based on a process in which each interleaved index is a function of an adjacent index. Based on the data block size (N) for a received data block and a constant (C) for the ARP interleaver, a plurality of interleaved indices is generated. For one embodiment in which the interleaved indices are generated in forward sequence, the adjacent interleaved index is the immediately previous index, P(j&#x2212;1), and each interleaved index (P(j)) is generated based on incrementing the previous interleaved index (P(j&#x2212;1)) by an incremental value k(i), where j represents a non-interleaved index between 0 and N&#x2212;1, i represents a modulo-C counter index that corresponds to j, k(i) represents the i-th value of a set of incremental values associated with N and C.

Efficient almost regular permutation (ARP) interleaver and method

A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.

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Dallas, TX, United States of America

Thomas M Henige