National Semiconductor Corporation

Motorola Corporation

Thomas M Frederiksen

Joseph J Connolly, Jr

Thomas P Redfern

William M Howard

Robert S Sleeth

William F Davis

Daniel D Culmer

James B Cecil

James L Dunkley

A differential amplifier is combined with a latch in a stage suitable for use in high speed comparators. An IC topography for the latch is also shown.

Bipolar strobed transistor latch for a high gain comparator

Butted guard band CMOS circuits have a typical breakdown of about 7 volts. It is often desirable to operate circuitry from supplies greater than 7 volts. For example, 9 volts is a commonly used supply value. An isolated zener diode is fabricated into a CMOS integrated circuit so as to develop a voltage drop equal to guard band breakdown. The zener voltage is coupled by way of a diode-connected transistor to the operating circuitry. The diode drop substracts from the zener voltage so that the circuitry is always operated at a voltage below its breakdown.

Zener regulator in butted guard band CMOS

A single chip integrated circuit analog-to-digital converter uses the successive approximation approach with resistor ladder-switching decoder digital-to-analog coverters coupled to a precision plural input comparator. An on board PROM is provided to store in digital form the information necessary to trim the digital-to-analog converters. The converter is actuated during wafer probing in the manufacturing process and the PROM is programmed with the trim information. Initially, the PROM is bypassed and the digital words needed for accurate trim applied externally. Once the correct trim words are found, the PROM is programmed with the correct words. A 13-bit converter is supplied with ten 7-bit trim words to achieve a fully trimmed product in wafer fabrication.

Digital error correcting trimming in an analog to digital converter

A detector for application to integrated circuits useful in determining the alignment of a trimming laser. A metallization pattern is employed along with electrical detection circuitry to determine when the trimming laser becomes misaligned by a predetermined amount. The laser is precision aimed when the integrated circuit wafer is located in a step and repeat machine. As stepping continues the detector provides an indication when the cumulative error exceeds the predetermined value.

Laser alignment detector

A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal. When a particular column is addressed, and the associated transistors in the address line turned on, all of the bits in the associated word will be 'ones.' The memory is programmed as desired after circuit manufacture in the wafer die sort operation by severing selected links with a laser beam. The severed device will program a 'zero' into the bit location. The word lines are coupled to a decoder that employs an array of gates having input pairs, one of which displays hysteresis. The memory also includes an external program simulation circuit which permits externally generating a particular digital word to simulate the memory content prior to programming.

Laser programmable read only memory

A high-gain, capacitor-coupled, chopper-stabilized, direct-current, voltage amplifier is capacitor coupled to a plurality of input switch pairs, each of which alternately couples one of a pair of input terminals to the amplifier. Thus, a voltage comparator results which has a plurality of pairs of inverting and non-inverting inputs. The relative contribution of the inputs can be weighted by ratioing the coupling capacitors of the switch pairs.

Precision plural input voltage amplifier and comparator

A plastic encapsulated integrated circuit (IC) package is disclosed which includes a conical depression or dimple precisely located over a photo-responsive semiconductor element incorporated within said integrated circuit for performing a predetermined function. The IC is encapsulated in a clear, two-part epoxy moulding compound preferably Hysol MG-18 having a tapered small depression positioned to register with the photo element but stopping short of actually touching the semiconductor photo element. Thus, the bottom of the tapered depression consists of a transparent window of sufficient thickness to protect the semiconductor element and still provide optical coupling. The minimum diameter of the light input depression located preferably at the top of the clear plastic package is designed to receive a snug fitting light pipe of Lucite or other clear material that could be used as a fiber optic element. The light pipe can be retained in the IC depression by mechanical means or optionally it can be cemented in place. A suitable light source for activating the photo-responsive semiconductor element in the IC may be a light emitting diode or an incandescent lamp.

Integrated circuit package with optical input coupler

A laser beam is employed to trim monolithic integrated circuits in wafer form in a step and repeat machine. The step and repeat action is adjusted to bring successive circuits on the wafer into trimming relationship with the laser. The circuit is measured and trimming accomplished to adjust the circuit performance to a precise specification. The step and repeat operation introduces a small error that accumulates as stepping proceeds. A laser beam error detector pattern is incorporated into the integrated circuit wafer and is designed to produce a response when the beam impingement error exceeds a predetermined value. The detector output causes the laser beam to be translated by an increment equal to the error and in the opposite direction. As a result, the laser beam aiming error is controlled by a known pattern rather than by an unknown cumulative error.

Laser beam error correcting process

The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.

Voltage translator for interfacing TTL and CMOS circuits

An improved comparator circuit is employed to respond to the charge on a capacitor which represents the integrated value of an input current. When the charge exceeds the comparator trip point, an output is generated. The output is delayed in time from the onset of the input current by an amount that is almost exactly linearly proportional to the current magnitude. The improvement comprises a circuit that senses the onset of comparator conduction and supplies the current necessary to operate the comparator. At very low input current values a condition can be reached where the current drawn by the comparator input equals or exceeds the applied current. For this condition an ordinary comparator will never trip. The improved circuit prevents this and, since the current added is only to compensate, the timing function is not seriously perturbed.

Extended range current-to-time converter

A differential amplifier has one input connected to a reference potential and a photo diode connected in series with a level shift to the other input. A negative feedback loop is also coupled into other input. This stabilizes the amplifier and, if the level shift is made equal to the reference potential, biases the photo diode to zero, thereby reducing leakage current. A second feedback loop is used to adaptively bias the tail current in the differential amplifier.

Adaptively biased differential operational amplifier for photo diode

A floating base transistor connected within an integrated circuit to provide a high temperature high voltage low current bypass device having the same type of temperature dependence as the leakage current shunted therethrough. The bypass device is connected to provide its I.sub.CEO current as a current source through which a parasitic leakage current is diverted which would otherwise produce a base current of an output transistor which is supposed to be in the off condition. The parasitic leakage current includes the I.sub.CEO current of an opposite polarity driving transistor in the off condition having its emitter connected to a power supply and its base connected to an input circuit and its collector connected to the base of the output transistor. In one embodiment the floating base transistor is a PNP substrate transistor having its collector connected to ground, its emitter connected to the base of an NPN output transistor, and its base floating. The current of the floating base transistor is greater than the parasitic leakage current of a PNP driving transistor, so the NPN output transistor is held in the off position.

Circuit utilizing open-base transistor as leakage bypass device

Current scaling in a lateral transistor wherein a plurality of emitter-collector circuits are established, certain of said circuits having a different base width than certain other of said circuits. In one embodiment, separate transistors are formed, each with its own emitter and collector, each portion of each collector being spaced an equal distance from its associated emitter the base widths of the different transistors being different, such that, with the emitters coupled in common, different currents being dependent on the base width of the associated transistor. In a second embodiment, a common emitter is employed with the separate collectors formed as arcs about the emitter, the base widths between the emitter and the different collectors being different.

Current scaling in lateral PNP structures

A sonar system utilizing a common LC tuned circuit for both the transmitter portion and the receiver portion of the electronic system so that both receiver and transmitter are tuned to the same frequency. The transducer is isolated from the LC tuned circuit so that the impedance characteristics of the transducer will not operate to change the main frequency of the tuned circuit. Thus interchangeable transducers may be utilized with the receiver-transmitter circuitry. The transmitter power pulses are generated by a novel Class C pulse circuit providing short time width, high intensity power pulses to the transducer.

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San Jose, CA, United States of America

Thomas M Frederiksen