International Business Machines Corporation

Thomas Ludwig

Joachim Keinert

Helmut Schettler

Edward J Nowak

Otto M Wagner

Brent A Anderson

Mark Alan Lavin

Jochen C Beintner

Juergen Koehl

Erich Klink

Wilhelm Ernst Haller

Holger Wetter

Ulrich Krauch

Werner O Haug

Rainer Zuhlke

Rainer Stahl

Ingo Aller

Karl E Kroll

Gunther W Kotzle

Qiqing Christine Ouyang

Fook-Luen Heng

BethAnn Rainey

Thomas-Michael Winkel

Gregory Allen Northrop

Robert T Sayah

Jin-Fuw Lee

Veit Gernhoefer

Heinz G Horbach

Juergen Haas

Volker Kreuter

Harald W Gruber

Fanchieh Yee

Mei-Kei Ieong

Rama Nand Sing

A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

Dense chevron finFET and method of manufacturing same

Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).

Circuit macro placement using macro aspect ratio based on ports

A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports.

Shaping ports in integrated circuit design

A method for creating a layout for design representation of an electronic circuit with at least one port. The method includes segmenting the at least one port in the design representation into different regions, classifying the different regions of the at least one port according to timing and/or electronic and/or layout characteristics, assigning a priority for each classified region of the at least one port according to rules based on the timing and/or electronic and/or layout characteristics, and routing the design representation by accessing at least one of the classified regions of the port according to an order of the assigned priorities.

Method, electronic design automation tool, computer program product, and data processing program for creating a layout for design representation of an electronic circuit and corresponding port for an electronic circuit

A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.

Gridded glyph geometric objects (L3GO) design method

An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number of routing tracks that may be connectable to that port. Routing priorities for the nets of the netlist may then be created using the port obscurity factors of the ports in the net. Routing may then be done in the order determined by the routing priority list and the generated layout information stored in a computer useable medium. In some cases, routing may be performed using multiple routing passes where a new routing priority list may be calculated for each routing pass.

Using port obscurity factors to improve routing

A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

Layout quality gauge for integrated circuit design

The present invention relates to a measurement arrangement for determining the characteristic line parameters by measuring the S-parameters as a function of the frequency of transmission lines. A voltage mesh and a ground mesh in a metal layer are connected symmetrically to a reference ground (RG) in the layer at all ends.

Measurement arrangement for determining the characteristic line parameters by measuring scattering parameters

A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.

Port assignment in hierarchical designs by abstracting macro logic

Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.

Field effect transistor with raised source/drain fin straps

In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.

Method and device for automated layer generation for double-gate FinFET designs

A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

Quasi self-aligned source/drain FinFET process

The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

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Sindelfingen, Germany

Thomas Ludwig