Analog Devices,inc.

Texas Instruments Corporation

Linear Technology Corporation

Other

Rockwell Automation Technologies Incorporated

Burr-brown Corporation

Dj Instruments

Thomas Lloyd Botker

Benjamin A Douts

Haoran Zhang

Rodney T Burt

Burt Sacherski

Yongyao Cai

Roberto S Santos

Yoshinori Kusuda

Timothy P Wolfe

Hubert John Biagi

Girish S Mali

Louis Panagotopulos

Vadium V Ivanov

John M Brown

Mali S Girish

An apparatus includes a casing defining a fluid flow channel, the casing including one or more diaphragms each defining a portion of the fluid flow channel, a strain gauge disposed on one of the one or more diaphragms, the strain gauge having a characteristic responsive to a pressure of fluid in the fluid flow channel, a temperature-sensitive circuit element disposed on one of the one or more diaphragms, the temperature-sensitive circuit element having a characteristic responsive to a temperature of the fluid in the fluid flow channel, and temperature compensation circuitry electrically coupled to the strain gauge and to the temperature-sensitive circuit element.

Temperature compensation of strain gauge output

An industrial locking switch comprises multiple locking tongue entry slots formed on adjacent sides of the locking switch housing, thereby supporting receipt of the corresponding locking tongue from multiple directions of approach without the need to mechanically modify the switch's head or to reorient the switch itself. The locking switch houses locking bolt detection circuity comprising multiple series connected RFID coils configured to detect an RFID tag mounted on the locking tongue when the locking tongue is inserted into any of the entry slots.

Guard locking switch with three concurrent directions of approach

An amplifier circuit has a voltage input terminal, for receiving Vin, and a voltage output terminal, for outputting Vout. A feedback circuit controls Vout to match Vin. A differential input stage receives Vin and Vout and generates a first output signal. An output stage comprises a pull down circuit for Vout. A main MOSFET is controlled by the first output signal to pull down Vout to match Vin when Vout is above a threshold voltage Vtrans. An auxiliary MOSFET, in parallel with the main MOSFET, is controlled by the first output signal to pull down Vout to match Vin when Vout is below Vtrans. The main MOSFET is turned substantially off when Vout is below Vtrans. A headroom generator coupled between the Vout terminal and a drain of the auxiliary MOSFET allows the auxiliary MOSFET to operate in its active region and pull Vout to ground.

Single supply amplifier with swing to ground

A driver for an analog-to-digital converter (ADC) has an overall feedback loop between its input and its output for maintaining overall accuracy, and a much faster feedback loop in its output stage that quickly compensates for output transients before the overall feedback loop can substantially react to the transients. Output voltage transients are created by the intermittent capacitive load of the ADC. The fast feedback loop can be made very fast since there are only a few components in the fast feedback path. The fast reduction of the output transients enables a shorter sampling time, leading to more accurate analog-to-digital conversion. The overall gain of the driver can be set to be greater than unity while still providing good output transient suppression.

Output stage with fast feedback for driving ADC

A method of improving the slew rate of an amplifier is described where a differential pair of transistors receives a differential first control signal and second control signal. The tail current for the transistors is provided by a tail current regulator. The same control signals are applied to a slew boost controller, whose output increases as the differential between the control signals increase. The tail current regulator generates a bias signal that sets a minimum tail current. The tail current is controlled to be the minimum tail current until the slew boost output signal exceeds a threshold, whereupon the tail current increases in response to an increasing differential between the control signals. Common mode rejection is not adversely affected by the slew boost controller generating a slightly varying current under common mode conditions due to the minimum tail current.

Translinear slew boost circuit for operational amplifier

A method of fabricating an instrumentation amplifier to have an improved common mode rejection ratio (CMRR) vs. frequency initially trims resistors in the input amplifiers of the instrumentation amplifier during a DC test, where the inputs are shorted and a DC voltage is applied, so that the output of the amplifier is approximately zero. This will normally cause the transconductances of the two input amplifiers to be different. Thus, the AC CMRR will degrade with frequency. Trimmable capacitors are provided in the input section and are trimmed during a common mode AC test to cause the output voltage to be minimized during the AC test. This causes the two input amplifiers to have the same bandwidth and gm/C ratio.

Common mode rejection ratio versus frequency in instrumentation amplifier

A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Auto-correction feedback loop for offset and ripple suppression in a chopper-stabilized amplifier

An amplifier front-end comprises an input node for receiving a common-mode voltage V, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage V, an error correction circuit, and a switching network. The switching network charges the capacitor to V; couples the capacitor to the differential pair's first input and couples Vto the pair's second input such that the voltage at both inputs is &#x2dc;V; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to &#x2dc;(V+V). The error correction circuit&#x2014;typically an auto-zero circuit&#x2014;is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Amplifier front-end with low-noise level shift

A current-mode instrumentation amplifier (IA) error reduction circuit and method employs a current-mode IA topology and an auto-zero circuit. The IA receives a differential voltage (VINP&#x2212;VINN) and produces differential DC currents (I, I) in response, which are summed to produce the amplifier's output current. Ideally, when VINP=VINN, Iand Iwill be equal; however, due to mismatches an error component Iwill be present such that I=I&#xb1;I. The auto-zero circuit is employed to reduce the magnitude of I. In operation, in an 'auto-zero mode', VINP and VINN are connected together and the auto-zero circuit operates to make I=I; a voltage needed to effect this is stored. Then, in 'normal mode', VINP and VINN are disconnected from each other and the IA is placed in the signal path, with the stored voltage acting to keep the magnitude of Ilow.

Current-mode instrumentation amplifier error reduction circuit and method

An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current I. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive I, and to provide the drive voltage to the bias current sources such that Iis maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

High CMR amplifier topology

A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current Ito a second node, the mirrored current (I) including a ripple current induced by the ripple voltage. A second current mirror is referred to the second node and mirrors a current Ito an output node, which provides a current Ito a load. The mirrors are sized such that the current provided at the second node is greater than the current required by the second mirror to provide I. The excess current, at least a portion of which includes a ripple component induced by the ripple voltage, is shunted to ground. As such, the magnitude of the ripple component in Iis less than that present in I

Ripple current reduction circuit

A chopper-stabilized current-mode instrumentation amplifier comprises first and second input amplifiers coupled to respective input nodes and arranged to produce respective currents in response to a differential input voltage applied to the input nodes; the currents are coupled to an output node. To reduce gain errors that might otherwise arise due to the parasitic capacitances of the on- and/or off-chip devices and/or structures making up the input amplifiers, the invention includes gain correction circuitry coupled to the IA. The gain correction circuitry replicates at least some of the parasitic capacitances, and provides compensation currents to the IA which reduce both input- and output-referred gain errors that might otherwise arise.

Current-mode instrumentation amplifier gain error correction circuitry

A current-mode instrumentation amplifier (IA) includes first and second buffer amplifiers which receive a differential voltage (VINP&#x2212;VINN) and provide output voltages at respective output nodes; a resistance Ris connected between the nodes and conducts a current Ithat varies with VINP&#x2212;VINN. In one embodiment, each amplifier includes a transistor connected in series with Rwhich conducts current I; these currents are coupled to the input and output terminals of a current mirror, preferably via respective virtual ground nodes such that the IA requires only one current mirror, to produce the IA's output voltage. To minimize DC mismatch errors, the IA is chopper-stabilized, with the buffer amplifiers and signal current paths chopped using a two-phase chopping cycle.

Current-mode instrumentation amplifier

A chopper-stabilized current mirror includes a pair of FETs connected to mirror an input current I. In one embodiment, switching networks Sand Shave their respective inputs connected to the FETs' drains, and are operated with clock signals CLKand CLK, respectively. An rboost amplifier Ahas its inputs connected to the outputs of Sand its outputs connected to the gates of a pair of cascode FETs via a switching network Swhich is operated with clock signal CLKS, with the drain of one cascode FET connected to Iand the drain of the other providing the mirror's output I. Sis clocked to reduce mismatch errors and Sand Sare clocked to reduce errors due to A's offset voltage, with CLKand CLKS shifted with respect to CLKto reduce errors due to parasitic capacitances.

Precision chopper-stabilized current mirror

A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit. In addition, the independent charging circuit includes an independent cell, and is local to charge pump circuit for supplying the current for charging the parasitic capacitances, instead of having the current supplied through external bussing or wire bonds.

Growing community of inventors

Andover, MA, United States of America

Thomas Lloyd Botker