Infineon Technologies Ag

Thomas Liebermann

Christoph Deml

Edvin Paparisto

Thomas Kern

Thomas Nirschl

Marc Tiebout

Rex Kho

Ulrich Backhausen

Jens Rosenbusch

Hans-Dieter Wohlmuth

Wolfgang Beck

Stephan Rogl

Werner Simburger

Michael Hassel

Jorg Langenberg

The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

System and method to store data in an adjustably partitionable memory array

A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.

Word line address scan

An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.

Integrated circuit having a memory arrangement

Integrated circuit including a mixer circuit, which has a first circuit section, a second circuit section, and a transformer. The first circuit section has two radiofrequency terminals. The second circuit section has two reference oscillator terminals, an active mixer unit with a signal-amplifying unit, and two intermediate frequency terminals. The active mixer unit and the signal-amplifying unit have a common current path. The transformer directly electrically decouples the two radiofrequency terminals from the active mixer unit, and couples the first circuit section and the second circuit section together such that each of the two circuit sections is separately supplied with a full operating voltage of the integrated circuit. The integrated circuit may additionally include a second transformer connected between the active mixer unit and the two intermediate frequency terminals.

Integrated circuit having a mixer circuit

A method for erasing or programming a nonvolatile memory device comprising a memory cell, a sense amplifier, and a page memory, the method comprising the steps of: performing an erasure or programming operation in a manner dependent on the data stored in the page memory, reading out the content of the erased or programmed memory cells, modifying the content of the page memory in a manner dependent on the data read out, and performing a further erasure or programming operation in a manner dependent on the modified data, and the data read out from the erased or programmed memory cell being fed to the page memory, and the content of the page memory being modified in a manner solely dependent on these data and control signals controlling the temporal sequence.

Nonvolatile memory device for storing data and method for erasing or programming the same

Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (), at least one source line (), at least one bit line (), at least one sense amplifier () and at least one precharge potential, the bit line () continuously having the precharge potential in a deselected state of the bit line (), and the source line () having a predetermined reference potential, in particular a ground potential (), in a selected state of the bit line ().

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Munich, Germany

Thomas Liebermann