Infineon Technologies Ag

Thomas Leitner

Daniel Kehrer

Paulo Oliveira

Johannes Meusburger

Joachim Fliesser

Andreas Wickmann

Hans-Dieter Wohlmuth

Daniel Schroegendorfer

Daniel Schrögendorfer

In accordance with an embodiment, a system includes a switchable resistive element configured to be coupled to an input of an RF amplifier, and a switchable capacitive element having a first terminal configured to be coupled between the switchable resistive element and inductive element coupled to a system input. The switchable capacitive element is configured to reduce a first impedance of the inductive element to a second impedance lower than the first impedance during a first operation mode; the switchable resistive element is configured to reduce an input impedance of the RF amplifier to a third impedance lower than the input impedance of the RF amplifier during the first operation mode; and the switchable capacitive element and the switchable resistive element are configured to provide a first attenuation to an RF signal provided at the system input during the first operation mode.

Circuitry, circuit module, system and method for impedance matching and signal attenuation

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

Instant RF overvoltage protection element

In accordance with an embodiment, a radio frequency (RF) amplifier circuit includes a switchable capacitance circuit having a first terminal configured to be coupled to an input matching inductor. The switchable capacitance circuit is configured to provide a short circuit between the first and second terminals in a first state, and provide a first capacitive impedance between the first and second terminals in a second state. The RF amplifier also includes a low noise amplifier (LNA) having an input terminal coupled to the second terminal of the switchable capacitance circuit; and a bypass switch coupled to an output of the LNA, the second terminal of the switchable capacitance circuit, and an output of the RF amplifier circuit. The bypass switch is configured to select the output of LNA in the first state, and select the second terminal of the switchable capacitance circuit in the second state.

System and method for bypassing a low noise amplifier

An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.

System and method for a low noise amplifier

In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively.

System and method for a bus interface

Embodiments of the invention show a bias circuit for providing a biasing signal at a bias connection. The bias circuit includes a bias transistor and a feedback node, wherein the feedback node is coupled to a control terminal of the bias transistor via a first impedance element. The feedback node is furthermore coupled to the bias connection via a second impedance element. The control terminal of the bias transistor is coupled to the bias connection via a bypass-coupling path, which bypasses the first impedance element and the second impedance element, such that there is a feedback path via the bypass-coupling path and via the bias transistor from the bias connection to the feedback node.

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Pregarten, Austria

Thomas Leitner