General Electric Company

United States of America As Represented by the Secretary of the Air Force

Polaroid Corporation

Thomas L Vogelsong

Jerome Johnson Tiemann

William E Engeler

Sharbel E Noujaim

Steven G Karr

Kenneth Brakeley Welles

Matthew N O'Donnell

Dale M Brown

Gerald J Michon

Richard D Baertsch

Manjin J Kim

Robert D Lillquist

Joseph M Pimbley

James R Toker

Selim S Bencuya

James Robert Toker

A charge injection imaging device comprises low bandwidth, low noise performance column amplifiers serially connected to respective charge coupled device storage lines. Image and/or noise defining electronic information signals are retrieved from the charge injection imaging device by way of the amplifiers and storage lines in a manner which provides image defining electronic information signals from which the noise defining electronic information signal portions have been automatically subtracted for each succeeding photosensitive element of the device. The subtracted noise portions include both KTC noise and fixed pattern noise which are normally inherently associated with the image defining electronic information signals retrieved from the charge injection imaging device.

Charge injection device with low noise readout

A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

Method and apparatus for high speed digital phased array coherent

An ultrasonic imaging processing system includes transducers and means to generate in an analog fashion, in-phase and quadrature phase signals. These signals are converted to digital form and a butterfly phase rotator circuit is employed to correct for phase differences in beam steering and focusing. In particular, speed and simplicity is achieved through the utilization of read only memory means providing appropriate function values for phase correction in conjunction with digital multiplication and summing circuitry.

Architecture for ultrasonic imaging

A charge-injection-device imager, having reduced crosstalk in a two-dimensional array of pixels each of which stores charge responsive to impingent light photons and until injection occurs, has: a column scanner for cyclically scanning each successive column of the array for each row to be scanned; a row scanner for cyclically scanning each successive row of the array, with each row being enabled after the conclusion of an injection time interval which appears after a previous row has been scanned, and also for re-scanning that row again while a second-next row is being scanned; line delay storage for the video signal provided by two successively scanned rows; and a subtractor for providing an imager output signal as the difference between the stored video signal from any row and the video signal from that same row after the stored charge of that row of pixels has been injected out of that row of pixels only after the next row had already been readout. A method for reducing crosstalk in a charge-injection-device imager of this type is also disclosed.

CID imager with reduced crosstalk and method for operation thereof

Multispectral imaging apparatus for producing a composite visible/infrared image includes a wavelength-independent focus reflective optical system for focusing visible and infrared radiation from a scene onto a hybrid visible/infrared radiation detector. The detector comprises an array of visible radiation responsive elements interspersed with infrared radiation responsive elements and provides first and second output signals corresponding, respectively, to the visible and the infrared radiation impinging upon the detector. The first and second signals are converted to a visible black and white image of the scene and a step-tone false color infrared image of the scene. The images are combined in exact spatial registration to produce a composite image comprising a visible image of the scene which is highlighted by the infrared radiation emitted by the scene.

Composite visible/thermal-infrared imaging system

A capacitor structure which is particularly suitable for use in analog integrated circuit devices employs an intermediate layer of a refractory metal disposed in a thin layer overlying a flat dielectric surface. The thinness and the low reflectivity of the refractory metal facilitates precise patterning of the upper plate of the capacitor structure. In the present invention, capacitance is no longer determined by imprecise cuts through thick oxide layers or by patterning of thick metallization layers within these apertures. The use of refractory metals in the capacitor structure also readily permits the incorporation of resistive circuit elements.

Refractory metal capacitor structures, particularly for analog

Programmable signal processing apparatus for multiplying a sampled analog signal by a multiple bit digital word coefficient. All signal processing operations are accomplished by the splitting, routing and combining of charge packets formed in a charge domain device.

Parallel programmable charge domain device

Pipelined programmable charge domain device

The signal processing apparatus includes a plurality of multiplying or charge splitting stages connected in series. A plurality of pairs of control words are provided, one word of each pair being the complement of the other word of the pair. Each pair of words is associated with a respective multiplying stage and represents the multiplying coefficient of a respective multiplying stage. Means are provided for forming a plurality of quantities of charge, each representing a respective sample of an analog signal. Each of the quantities of charge is introduced in sequence into each of the multiplying stages in which it is processed and then passed on to the next multiplying stage. The process operation in each of the multiplying stages includes dividing the quantity of charge in a series of splitting operations under the control of the pair of words associated with the stage into two parts. All of the first parts of each of the quantities of charge in each of the stages is summed. All of the second part of each of the quantities of charge in each of the stages is summed. A signal is derived representing the difference of the two sums of charge. The two parts of each quantity of charge are combined and passed to the next multiplying stage.

Charge transfer multiplier and filter

A charge transfer filter utilizing a charge transfer accumulator structure for exponential smoothing of sampled data signals is described. The charge transfer accumulator structure performs charge equilibration at high speed thereby enabling an exponential decay impulse response to be obtained at high speed.

Charge transfer filter structure including a splitter and equilibrator

A filter utilizing charge transfer devices for providing recursive transfer functions is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, a first charge transfer shift register, and a second charge transfer shift register. A first input stage is unidirectionally coupled to the first stage of the first shift register and is also bidirectionally coupled to the N.sup.th stage of the circular shift register. A second input stage is unidirectionally coupled to the first stage of the second shift register and is also bidirectionally coupled to the (N/2).sup.th stage of the circular shift register. A first input sequence of packets of charge representing positive weight components of a signal is applied to the first input stage and a second input sequence of packets of charge representing negative weight components of the signal is applied to the second input stage. All three shift registers are clocked at the same frequency. At the end of each clocking cycle the charge stored in the N.sup.th stage of the circular shift register and in the first input stage are combined and divided into a first part contained in the first input stage, and a second part which is contained in the N.sup.th stage of the circular shift register. The first part of the combined charge is clocked into the first shift register and clocked from stage to stage thereof. The second part of the combined charge is clocked from stage to stage of the circular shift register. Similarly, at the end of each clocking cycle the charge stored in the (N/2).sup.th stage of the circular shift register and in the second input stage are combined and divided into a first part contained in the second input stage, and a second part which is contained in the (N/2).sup.th stage of the circular shift register. The first part of the combined charge is clocked into the second shift register and clocked from stage to stage thereof. The second part of the combined charge is clocked from stage to stage of the circular shift register. Charge division and collection means are provided at the various stages of the first shift register to divide and collect fractions of charge appearing in the various stages thereof. The charge collection means of the various stages are connected together and provide a first output sequence of packets of charge representing the positive components of an output signal. The aforementioned fractions represent the weighting coefficients of the various stages of the first shift register. The second charge transfer shift register is identical to the first shift register. The charge collection means of the various stages of the second shift register are also connected together and provide a second output sequence of packets representing the negative components of the output signal.

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Schenectady, NY, United States of America

Thomas L Vogelsong