International Business Machines Corporation

Motorola Corporation

Freescale Semiconductor,inc.

Thomas L Thomas, Jr

Terence M Potter

Christopher Hans Olson

Jose Melanio Nunez

James Andrew Welker

Paul C Rossbach

Thomas Alan Hoy

Robert Thaddeus Golla

Daniel W Knox

An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Method and apparatus for skewing data with respect to command on a DDR interface

A clock distribution and control system () includes one counter () in a clock generation domain and another counter () in a phase-delayed clock domain. The phase-delayed domain counter () output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

System and method for deterministic communication across clock domains

A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

Processor having a selectively configurable branch prediction unit that

A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.

Method and system for dynamically recovering a register-address-table

The disclosed data processor (10) has a future file (60) for providing the most recent value of a set of architectural registers (32, 36) to the various execution units (20, 22, 24, 26, 28, 30) of the data processor. The most recent value of the set of architectural registers is determined with respect to the original instruction sequence. The future file provides a single source for operand look-up at instruction dispatch and can be corrected in a single cycle in the event of an exception condition.

Growing community of inventors

Austin, TX, United States of America

Thomas L Thomas, Jr