Intel Corporation

Thomas L Sounart

Feras Eid

Johanna M Swan

Shawna M Liff

Sasha N Oster

Aleksandar Aleksov

Georgios C Dogiamis

Adel A Elsherbini

Valluri Ramana Rao

Baris Bicen

Henning Braunisch

Kristof Darmawikarta

Andrew James Brown

Anup Pancholi

Prithwish Chatterjee

Sansaptak W Dasgupta

Khaled Ahmed

John Heck

Srinivas V Pietambaram

Kaan Oguz

Vijay K Nair

Suddhasattwa Nad

Neelam Prabhu Gaunkar

Harel Frish

I-Cheng Tung

Darko Grujicic

Marcel Arlan Wall

Benjamin Duong

Sashi S Kandanur

Rengarajan Shanmugam

Jelena Culic-Viskota

Helme A Castro De La Torre

Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Substrate integrated thin film capacitors using amorphous high-k dielectrics

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Cooling of conformal power delivery structures

A micro-light emitting diode (LED) display and a method of fabricating the same. The method includes aligning a display backplane and a source semiconductor wafer with one another. A plurality of backplane contact pads of a first width are fixed to the backplane and include first solder pads thereon with a second width smaller than the first width. The wafer includes thereon a plurality of micro-LEDs, and a plurality of micro-LED contact pads fixed to the micro-LEDs and having a third width smaller than the first width. The method includes: aligning such that at least some of the micro-LED contact pads register with corresponding first solder pads; releasing at least some of the micro-LEDs from the wafer onto corresponding first solder pads; and forming a plurality of second solder pads by melting the corresponding first solder pads. The second solder pads bond the at least some of the micro-LEDs to corresponding ones of the plurality of backplane contact pads, the second solder pads further extending on said corresponding ones of the plurality of backplane contact pads beyond a footprint thereon of said some of the micro-LEDs.

Micro-LED displays including solder structures and methods

Electronics package device technology is disclosed. In one example, an electronics package device () comprises substrate () supporting an electronics component () and an interconnect via (-) electrically coupled to the electronics component such that at least a portion of the electronics component is disposed between the interconnect via and the substrate. The interconnect via can be directly coupled to the electronics component such that the interconnect via and the electronics component are vertically disposed between a second electronics package device () and the substrate. A second electronics package device can be stacked to the first electronics package device, and can comprise similar architecture of the interconnect via attached to the electronics component as with the first electronics package. Thus, 3D package size is significantly reduced. Associated systems and processes are disclosed.

Architectures and methods of fabricating 3D stacked packages

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Low leakage thin film capacitors using titanium oxide dielectric with conducting noble metal oxide electrodes

An semiconductor manufacturing apparatus and method to smooth surfaces of discrete pads on a substrate. The method includes placing a surface of one of the discrete pads in registration with a first chamber of a set of chambers of a smoothing tool, the set corresponding to a smoothing cycle of the smoothing tool; etching, within the first chamber, a surface of one of the discrete pads to form an etch layer on the surface; placing the surface in registration with a second chamber of the set; after the etch, pumping gas and vapor from the surface within the second chamber; placing the surface in registration with a third chamber of the set; and applying heating to the surface in the third chamber to smooth the surface.

Semiconductor smoothing apparatus and method

A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

III-N multichip modules and methods of fabrication

Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.

In situ package integrated thin film capacitors for power delivery

Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.

Inorganic piezoelectric materials formed on fibers and applications thereof

Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.

Microelectronic assemblies having substrate-integrated perovskite layers

Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the second electrical component. In an embodiment the encryption bank may include a plurality of portions that each have one or more switches integrated into the package substrate. In an embodiment each sensor transmits data to the second electrical component along different portions of the encryption bank. In some embodiments, the switches may be piezoelectrically actuated. In other embodiments the switches may be actuated by thermal expansion. Additional embodiments may include tri- or bi-stable mechanical switches.

Growing community of inventors

Scottsdale, AZ, United States of America

Thomas L Sounart