International Business Machines Corporation

Globalfoundries Inc.

Other

Thomas L McDevitt

Anthony K Stamper

Jeffrey P Gambino

Felix Patrick Anderson

Edward Crandal Cooney, Iii

Stephen Ellinwood Luce

Timothy Harrison Daubenspeck

Hyun K Lee

William Thomas Motsiff

Baozhen Li

William Joseph Murphy

Jonathan Daniel Chapple-Sokol

Arthur C Winslow

John E Heidenreich, Iii

William R Hill

Robert Zwonik

Terence B Hook

Zhong-Xiang He

Timothy Dooling Sullivan

Jeffrey Scott Zimmerman

Eva A Shah

Steven P Barkyoumb

Kenneth E McAvey, Jr

Christopher A Ponsolle

Bette B Reuter

David V Horak

John Anthony Fitzsimmons

Eric Jeffrey White

Kwong Hon Wong

Gregory Costrini

Lee Matthew Nicholson

William A Klaasen

Henry Atkinson Nye, Iii

Ronald Dean Goldblatt

Keith Edward Downes

David Craig Strippe

Henry W Trombley

Lloyd G Burrell

Graham M Bates

Mark P Murray

Mark D Levy

Sally J Yankee

Timothy S Hayes

Jennifer C Robbins

Donald R Letourneau

Scott L Pennington

Mark J Pouliot

Edward E Cooney, Iii

Daniel C Edelstein

Julio C Costa

Xiao Hu Liu

Tom C Lee

Paul Christian Parries

James Gardner Ryan

William J Cote

Jonathan Hale Hammond

Gary L Milo

Matthew T Tiersch

Thomas J Licata

Yoba Amoah

Kenneth F McAvey, Jr

Pei-ing P Lee

Stephen E Knight

Joseph P Hasselbach

Michael A Smey

Gregory S Chrisman

Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.

Integrated circuit switches, design structure and methods of fabricating the same

A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.

Curvilinear wiring structure to reduce areas of high field density in an integrated circuit

Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.

Methods of manufacturing semiconductor devices and a semiconductor structure

A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.

System and method for forming an aluminum fuse for compatibility with copper BEOL interconnect scheme

System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme

A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.

Horizontal coplanar switches and methods of manufacture

Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

Vertical integrated circuit switches, design structure and methods of fabricating same

A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.

Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

Structure and method for reducing vertical crack propagation

Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.

Electrical fuse with a current shunt

A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.

Top corner rounding of damascene wire for insulator crack suppression

A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.

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Underhill, VT, United States of America

Thomas L McDevitt