Motorola Corporation

Motorola Solutions, Inc.

Thomas L Gradishar

Robert E Stengel

Nicholas Giovanni Cafaro

Stephen T Machan

A frequency generator () takes a signal source (clock or carrier) () and generates a edge encoded direct digital modulated differential output signal (). The differential signal () is applied to a frequency extension quadrature generator (FEQG) (). The FEQG () includes a fractional differential wavelength delay locked loop (DLL) () and a frequency multiplier (). The DLL () generates a control voltage () with which to control delays of the edge encoded modulation signal (). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (), to provide the output signal set

Method and apparatus for reconfigurable frequency generation

A DPC () includes: a frequency source () for generating a clock signal; a delay line () for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device () for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices () and a combining network. A method for use in a DPC includes: receiving () a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting () at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating () an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Method and apparatus for a digital-to-phase converter

Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Direct digital synthesizer with variable reference for improved spurious performance

A direct digital synthesizer (DDS) () that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (). The DDS () includes one or more dither sources () and a random access memory (RAM) (). The RAM () utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source () to compensate unequal unit delay values in the DTC ().

System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis

A direct digital synthesizer () with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer () and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter () and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal () to the quantizer and an output signal () from the quantizer. The ROM-less direct digital synthesizer can further include a dither () combined at an input of the quantizer.

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Boynton Beach, FL, United States of America

Thomas L Gradishar