Infineon Technologies Ag

Thomas Kurzmann

Holger Ruething

Oliver Humbel

Angelika Koprowski

Josef-Georg Bauer

Erwin Lercher

Philipp Sebastian Koch

Jens Brandenburg

Diana Car

Sebastian Kremp

A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 &#x3bc;m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.

Ppower semiconductor device with anticorrosive edge termination structure

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Villach, Austria

Thomas Kurzmann