Advanced Micro Devices Corporation

Ati Technologies Ulc

Thomas Kunjan

Frank Barth

Joerg Winkler

John Kalamatianos

Maurice B Steinman

Jonathan Mercer Owen

Guhan Krishnan

Antonio Asaro

Ralf Flemming

Don Cherepacha

Marius Evers

Krishnan V Ramani

Scott Thomas Bingham

Jörg Winkler

A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

Processor with accelerated lock instruction operation

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Hierarchical memory arbitration technique for disparate sources

A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

Combined command and response on-chip data interface for a computer system chipset

An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for edge triggered interrupt messages on the basis of the request occurrence signals. An interrupt termination detection unit receives termination signals each indicating that an interrupt routine relating to a previous edge triggered interrupt message has terminated. The interrupt input unit is controlled to output a request occurrence signal in response to a received termination signal if a previously received level sensitive interrupt request is still active. That is, a second edge triggered interrupt message may be generated.

Message based transport mechanism for level sensitive interrupts

A command storage technique that fulfils ordering rules is provided. This technique may be used in HyperTransport compliant southbridge devices. A command transmit engine comprises a command storage unit that is adapted to receive incoming commands of different command types and store the command in the order in which the commands were received. The command transmit engine further comprises an ordering rule controller that is connected to the command storage unit to select stored commands to be transmitted. The ordering rule controller is adapted to perform the selection according to predefined command ordering rules. The command ordering rules are command type dependent.

Ordering rule controlled command storage

An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit can store data relating to a request to be sent, and the second circuit unit cannot store data relating to a received request. Thus, an on-chip interface is provided that may increase the overall system performance and that may support split transaction.

Growing community of inventors

Dresden, Germany

Thomas Kunjan