National Semiconductor Corporation

Thomas Klein

Charles E Boettcher

Andrew G Varadi

An improved dynamic MOS RAM having a plurality of selection lines and data lines and a plurality of storage cells connected thereto, wherein each storage cell includes a storage capacitor having first and second plates, wherein the second plate is adapted to be coupled to a reference potential terminal; and a MOSFET having a semiconductor substrate, a gate connected to one of the selection lines, a first conduction terminal coupled to one of the data lines, and a second conduction terminal connected in common with a first plate of the storage capacitor, is disclosed. The first plate of the storage capacitor includes first doped polysilicon conductive layer that has the majority of its area separated from the semiconductor substrate of the MOSFET by at least an insulating layer. The second plate of the storage capacitor includes a second doped polysilicon conductive layer that is at least coextensive with and insulated from the first conductive layer. The transistor gate is defined by a third doped polysilicon conductive layer that is insulated from the first and second conductive layers. Approximately 45% of the cell area can be utilized for charge storage, and only about 20% of this storage area is susceptible to loss of charge by reason of leakage through the depletion/junction area in the substrate.

Dynamic MOS RAM with storage cells having a mainly insulated first plate

This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

Method for making a semiconductor capacitor

Method of making integrated semiconductor structure having an MOS and a

A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

Method of manufacturing a low voltage n-channel MOSFET device

A process for constructing self-aligned electrodes overlying a surface of a semiconductor substrate is disclosed. The process utilizes a substrate which is substantially transparent to infrared radiation. One step of the process includes forming spaced apart ones of the electrodes with a conductive material that is highly absorbtive of infrared radiation. Subsequently, a continuous layer of heat sensitive polymer is formed over and between these spaced apart electrodes. The resulting structure is exposed to infrared radiation which heats the spaced apart electrodes. This heat polymerizes the heat sensitive polymer layer in all regions that directly overlie the spaced apart electrodes. These polymerized regions form a mask that is used to construct other electrodes between and in alignment with the spaced apart electrodes.

Infrared photolithographic process for constructing self-aligned

An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface. Contact cuts are made through the phosphosilicate glass through which metal contacts are established.

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Saratoga, CA, United States of America

Thomas Klein