Arm Limited

Thomas Kelshaw Conway

Martinus Cornelis Wezelenburg

Michael Andrew Campbell

An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction. The decoding circuitry comprises error correction circuitry configured, for each read code word, to perform an error correction process to detect and correct errors in up to P symbols of the code word, where P is dependent on the number of ECC symbols in the code word. Error tracking circuitry determines error quantity indication data indicative of the errors detected by the error correction circuitry, and in response to the error quantity indication data indicating that an error threshold condition has been reached, the apparatus transitions from a normal mode of operation to a safety mode of operation.

Apparatus and method for controlling access to a memory device

An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient.

Error correction for multilevel flash memory

An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P&#x2212;(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.

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Cambridge, United Kingdom

Thomas Kelshaw Conway