International Business Machines Corporation

Thomas Kalla

Juergen Pille

Jens Noack

Philipp Salz

Albert Frisch

Hans-Werner Anderson

Uwe Brandt

Markus Buehler

Holger Wetter

Monika Strohmer

Katherine Eve

Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.

Build synthesized soft arrays

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.

Activation of memory core circuits in an integrated circuit

Embodiments of the present invention provide systems and methods for reducing power consumption during the operation of a SRAM cell. Embodiments of the present invention reduce power consumption by determining switching activity, and based off a determination of low switching activity, gates off a core which is not written; and limits switching activity on the unaddressed core by applying the highest order bit.

NAND-based write driver for SRAM

A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.

Parsing data representative of a hardware design into commands of a hardware design environment

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Boeblingen, Germany

Thomas Kalla