Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Robert Boschgmbh

Thomas Kaempfe

Konrad Seidel

Patrick Polakowski

Tobias Kirchner

Taha Soliman

The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line () of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I, I, I) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I, I, I) into the third line () as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element () with a control terminal which is connected to the second line () of the corresponding column; wherein input voltages (U, U, U) corresponding to components of the input vector are applied () to the first lines; wherein for each column: a ramp voltage (V, V, V) is applied () to the second line assigned to the column, the level of which is increased with time (); a total current is detected at the third line assigned to the column and a time period elapsed since a start time of the level increase of the corresponding ramp voltage is determined () until the magnitude of the total current reaches a certain current magnitude threshold (Ig) (); and a component of the output vector corresponding to the column is determined () based on the elapsed time period (t, t, t).

Method for mapping an input vector to an output vector by means of a matrix circuit

The present invention relates to an integrated electronic circuit and method of making comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

Integrated electronic circuit and method of making comprising a first transistor and a ferroelectric capacitor

The present invention relates to a voltage-controllable capacitor comprising a first electrode layer () composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (), a ferroelectric interlayer () having a thickness that is less than the thickness of the first electrode layer (), and a second electrode layer () composed of a non-ferroelectric material. The ferroelectric interlayer () is arranged between the first electrode layer () and the second electrode layer ().

Voltage-controllable capacitor comprising a ferroelectric layer and method for producing the voltage-controllable capacitor comprising a ferroelectric layer

The present invention relates to an integrated electronic circuit comprising a first transistor () and a ferroelectric capacitor (). The ferroelectric capacitor () comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor ().

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Dresden, Germany

Thomas Kaempfe