Motorola Corporation

Freescale Semiconductor,inc.

Freescale Semiconductors Inc.

Thomas K Johnston

Grady L Giles

William Daune Atwell

John J Vaglica

David Russell Tipple

Bernard J Pappert

Frank David Frederick

John Mark Boyer

William Clayton Bruce, Jr

An adjustable buffer including a series of P-channel devices having current paths coupled between a first voltage supply and at least one output node, and a series of N-channel devices having current paths coupled between the output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the output node. The selectable connections may be defined in an integrated circuit mask or may be electronic switches. The P- and N-channel devices may be in a balanced configuration or an imbalanced configuration. The P- and N-channel devices may form an inverting buffer or a non-inverting buffer.

Clock tree adjustable buffer

An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.

Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

Scan clock circuit and method therefor

A BIST controller (,) and methodology uses the DRAM controller (,) refresh signals to test the data retention characteristics of a DRAM memory array (,). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM's specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM's refresh interval.

Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry

A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.

Method and apparatus for leveraging history bits to optimize memory

A method and system for performing memory repair via redundant rows of memory uses memory elements (208 and 210) for redundant row selection instead of conventional fuses. An on-chip test controller (110) is capable of testing memory rows (106) either at wafer probe, at final testing after manufacturing, or after memory chip packaging and/or final sale to end users. If this testing identifies faulty memory rows in the memory array at any time, the electrically programmable memory elements (208 and 210) can be internally re-programmed to create a new memory configuration which includes redundant memory rows (108). This new memory configuration is enabled in order to remove the newly-detected and previously-detected faulty memory rows from active memory in the memory array.

Fusleless memory repair system and method of operation

A method and apparatus for allowing an integrated circuit to be hard-wired into one of a plurality of modes of operation by providing a plurality of mode bonding pads (104-108). Based upon customer demand, a reset post (102) or like external terminal of the integrated circuit is wire bonded or conductively coupled to only one of the plurality of mode pads (104-108). By bonding only one of the mode pads (104-108) to the reset pin, one of the plurality of distinct modes of operation is enabled upon reset.

Integrated circuit for external bus interface having programmable mode

A counter (200) generates signals which have an average period of a non-integer multiple of an input clock period. Through the use of this non-integer multiple period, non-integer division operations are executed and used in circuits such as pulse width modulators (800) and phase lock loops (900). Additionally, when the counter (200') is used with a Gray coded counter, the average duty cycle of all bits is exactly equal to 50%.

Growing community of inventors

Austin, TX, United States of America

Thomas K Johnston